27 lines
405 B
Verilog
27 lines
405 B
Verilog
module bin_to_bcd(
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input wire[7:0] bin,
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output reg[11:0] bcd);
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integer i;
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always @(bin) begin
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bcd = 0;
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for (i = 0; i < 8; i = i+1) begin
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if (bcd[3:0] > 4)
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bcd[3:0] = bcd[3:0] + 3;
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if (bcd[7:4] > 4)
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bcd[7:4] = bcd[7:4] + 3;
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if (bcd[11:8] > 4)
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bcd[11:8] = bcd[11:8] + 3;
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// Concatenate acts as a shift
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bcd = {bcd[10:0], bin[7-i]};
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end
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end
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endmodule
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