68 lines
1.2 KiB
Verilog
68 lines
1.2 KiB
Verilog
`include "cpu.v"
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`include "7seg.v"
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`include "bin_to_bcd.v"
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module top(
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input CLK,
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input PIN_13,
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output PIN_9,
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output PIN_10, output PIN_11,
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output PIN_12, output PIN_14,
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output PIN_15, output PIN_16,
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output PIN_17, output PIN_18,
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output PIN_19, output PIN_20);
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reg[7:0] out;
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reg[23:0] clk;
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always @(posedge CLK)
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clk <= clk + 1;
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cpu cpu0(
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.clk(clk[15]),
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.reset(PIN_13),
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.out(out));
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reg[3:0] cathode = 4'b1110;
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reg[6:0] seg_ones;
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reg[6:0] seg_tens;
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reg[6:0] seg_hundreds;
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wire[11:0] bcd;
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bin_to_bcd bin_to_bcd0(out, bcd);
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seven_seg seven_seg_ones(
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.bcd(bcd[3:0]),
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.segments(seg_ones));
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seven_seg seven_seg_tens(
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.bcd(bcd[7:4]),
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.segments(seg_tens));
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seven_seg seven_seg_hundreds(
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.bcd(bcd[11:8]),
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.segments(seg_hundreds));
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always @(posedge clk[10])
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case (cathode)
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4'b1110: begin
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cathode = 4'b1011;
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{PIN_11, PIN_9, PIN_15, PIN_18, PIN_19, PIN_10, PIN_14} = seg_hundreds;
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end
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4'b1011: begin
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cathode = 4'b1101;
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{PIN_11, PIN_9, PIN_15, PIN_18, PIN_19, PIN_10, PIN_14} = seg_tens;
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end
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4'b1101: begin
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cathode = 4'b1110;
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{PIN_11, PIN_9, PIN_15, PIN_18, PIN_19, PIN_10, PIN_14} = seg_ones;
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end
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default: begin
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cathode = 4'b1111;
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end
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endcase
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assign {PIN_20, PIN_17, PIN_16, PIN_12} = cathode;
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endmodule
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