22 lines
409 B
Verilog
22 lines
409 B
Verilog
module seven_seg(
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input wire[3:0] bcd,
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output wire[6:0] segments
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);
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assign segments =
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// ABCDEFG
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(bcd == 0) ? 7'b1111110 :
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(bcd == 1) ? 7'b0110000 :
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(bcd == 2) ? 7'b1101101 :
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(bcd == 3) ? 7'b1111001 :
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(bcd == 4) ? 7'b0110011 :
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(bcd == 5) ? 7'b1011011 :
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(bcd == 6) ? 7'b1011111 :
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(bcd == 7) ? 7'b1110000 :
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(bcd == 8) ? 7'b1111111 :
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(bcd == 9) ? 7'b1110011 :
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7'b0000000;
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endmodule
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