From 87677036174063bd2f85110d76c3238ad57cf408 Mon Sep 17 00:00:00 2001
From: Austin Morlan <mail@austinmorlan.com>
Date: Thu, 30 Sep 2021 18:47:08 -0700
Subject: [PATCH] Initial commit

---
 README.md          |  10 +
 build.sh           |  13 +
 code/constants.inc |  24 ++
 code/hardware.inc  | 913 +++++++++++++++++++++++++++++++++++++++++++++
 code/main.asm      | 731 ++++++++++++++++++++++++++++++++++++
 code/ops.asm       | 259 +++++++++++++
 code/signals.asm   | 254 +++++++++++++
 code/tick.asm      | 294 +++++++++++++++
 8 files changed, 2498 insertions(+)
 create mode 100644 README.md
 create mode 100755 build.sh
 create mode 100644 code/constants.inc
 create mode 100644 code/hardware.inc
 create mode 100644 code/main.asm
 create mode 100644 code/ops.asm
 create mode 100644 code/signals.asm
 create mode 100644 code/tick.asm

diff --git a/README.md b/README.md
new file mode 100644
index 0000000..0fcd4c5
--- /dev/null
+++ b/README.md
@@ -0,0 +1,10 @@
+# Breadboard Game Boy
+
+A Game Boy version of the 8-bit computer built by Ben Eater in his [series of videos](https://eater.net/8bit).
+
+[Here is a blog post about it.](https://austinmorlan.com/posts/8bit_breadboard_gameboy/)
+
+![Emulator Demo](https://austinmorlan.com/posts/8bit_breadboard_gameboy/media/count_emu.gif)
+
+![Hardware Demo](https://austinmorlan.com/posts/8bit_breadboard_gameboy/media/count_hw.gif)
+
diff --git a/build.sh b/build.sh
new file mode 100755
index 0000000..296e9d2
--- /dev/null
+++ b/build.sh
@@ -0,0 +1,13 @@
+#!/usr/bin/env bash
+
+CODE_DIR=code
+BUILD_DIR=build
+TEMP_DIR=$BUILD_DIR/temp
+
+GAME_NAME=8bit
+
+mkdir -p $TEMP_DIR
+rgbasm -Weverything -E -i $CODE_DIR -o $TEMP_DIR/$GAME_NAME.obj $CODE_DIR/main.asm
+rgblink -n $BUILD_DIR/$GAME_NAME.sym -m $BUILD_DIR/$GAME_NAME.map -o $BUILD_DIR/$GAME_NAME.gb $TEMP_DIR/$GAME_NAME.obj
+rgbfix -v -p0 $BUILD_DIR/$GAME_NAME.gb
+
diff --git a/code/constants.inc b/code/constants.inc
new file mode 100644
index 0000000..d625ccd
--- /dev/null
+++ b/code/constants.inc
@@ -0,0 +1,24 @@
+LED_OFF EQU $25
+LED_ON EQU $26
+
+CTRL_HT EQU 7
+CTRL_MI EQU 6
+CTRL_RI EQU 5
+CTRL_RO EQU 4
+CTRL_IO EQU 3
+CTRL_II EQU 2
+CTRL_AI EQU 1
+CTRL_AO EQU 0
+
+CTRL_EO EQU 7
+CTRL_SU EQU 6
+CTRL_BI EQU 5
+CTRL_OI EQU 4
+CTRL_CE EQU 3
+CTRL_CO EQU 2
+CTRL_JP EQU 1
+CTRL_FI EQU 0
+
+FLAG_C EQU 1
+FLAG_Z EQU 0
+
diff --git a/code/hardware.inc b/code/hardware.inc
new file mode 100644
index 0000000..376af3e
--- /dev/null
+++ b/code/hardware.inc
@@ -0,0 +1,913 @@
+;*
+;* Gameboy Hardware definitions
+;*
+;* Based on Jones' hardware.inc
+;* And based on Carsten Sorensen's ideas.
+;*
+;* Rev 1.1 - 15-Jul-97 : Added define check
+;* Rev 1.2 - 18-Jul-97 : Added revision check macro
+;* Rev 1.3 - 19-Jul-97 : Modified for RGBASM V1.05
+;* Rev 1.4 - 27-Jul-97 : Modified for new subroutine prefixes
+;* Rev 1.5 - 15-Aug-97 : Added _HRAM, PAD, CART defines
+;*                     :  and Nintendo Logo
+;* Rev 1.6 - 30-Nov-97 : Added rDIV, rTIMA, rTMA, & rTAC
+;* Rev 1.7 - 31-Jan-98 : Added _SCRN0, _SCRN1
+;* Rev 1.8 - 15-Feb-98 : Added rSB, rSC
+;* Rev 1.9 - 16-Feb-98 : Converted I/O registers to $FFXX format
+;* Rev 2.0 -           : Added GBC registers
+;* Rev 2.1 -           : Added MBC5 & cart RAM enable/disable defines
+;* Rev 2.2 -           : Fixed NR42,NR43, & NR44 equates
+;* Rev 2.3 -           : Fixed incorrect _HRAM equate
+;* Rev 2.4 - 27-Apr-13 : Added some cart defines (AntonioND)
+;* Rev 2.5 - 03-May-15 : Fixed format (AntonioND)
+;* Rev 2.6 - 09-Apr-16 : Added GBC OAM and cart defines (AntonioND)
+;* Rev 2.7 - 19-Jan-19 : Added rPCMXX (ISSOtm)
+;* Rev 2.8 - 03-Feb-19 : Added audio registers flags (Álvaro Cuesta)
+;* Rev 2.9 - 28-Feb-20 : Added utility rP1 constants
+;* Rev 3.0 - 27-Aug-20 : Register ordering, byte-based sizes, OAM additions, general cleanup (Blitter Object)
+
+; If all of these are already defined, don't do it again.
+
+    IF !DEF(HARDWARE_INC)
+HARDWARE_INC SET 1
+
+rev_Check_hardware_inc : MACRO
+;NOTE: REVISION NUMBER CHANGES MUST BE ADDED
+;TO SECOND PARAMETER IN FOLLOWING LINE.
+    IF  \1 > 3.0 ;PUT REVISION NUMBER HERE
+        WARN    "Version \1 or later of 'hardware.inc' is required."
+    ENDC
+ENDM
+
+_VRAM        EQU $8000 ; $8000->$9FFF
+_VRAM8000    EQU _VRAM
+_VRAM8800    EQU _VRAM+$800
+_VRAM9000    EQU _VRAM+$1000
+_SCRN0       EQU $9800 ; $9800->$9BFF
+_SCRN1       EQU $9C00 ; $9C00->$9FFF
+_SRAM        EQU $A000 ; $A000->$BFFF
+_RAM         EQU $C000 ; $C000->$CFFF / $C000->$DFFF
+_RAMBANK     EQU $D000 ; $D000->$DFFF
+_OAMRAM      EQU $FE00 ; $FE00->$FE9F
+_IO          EQU $FF00 ; $FF00->$FF7F,$FFFF
+_AUD3WAVERAM EQU $FF30 ; $FF30->$FF3F
+_HRAM        EQU $FF80 ; $FF80->$FFFE
+
+; *** MBC5 Equates ***
+
+rRAMG        EQU $0000 ; $0000->$1fff
+rROMB0       EQU $2000 ; $2000->$2fff
+rROMB1       EQU $3000 ; $3000->$3fff - If more than 256 ROM banks are present.
+rRAMB        EQU $4000 ; $4000->$5fff - Bit 3 enables rumble (if present)
+
+
+;***************************************************************************
+;*
+;* Custom registers
+;*
+;***************************************************************************
+
+; --
+; -- P1 ($FF00)
+; -- Register for reading joy pad info. (R/W)
+; --
+rP1 EQU $FF00
+
+P1F_5 EQU %00100000 ; P15 out port, set to 0 to get buttons
+P1F_4 EQU %00010000 ; P14 out port, set to 0 to get dpad
+P1F_3 EQU %00001000 ; P13 in port
+P1F_2 EQU %00000100 ; P12 in port
+P1F_1 EQU %00000010 ; P11 in port
+P1F_0 EQU %00000001 ; P10 in port
+
+P1F_GET_DPAD EQU P1F_5
+P1F_GET_BTN  EQU P1F_4
+P1F_GET_NONE EQU P1F_4 | P1F_5
+
+
+; --
+; -- SB ($FF01)
+; -- Serial Transfer Data (R/W)
+; --
+rSB EQU $FF01
+
+
+; --
+; -- SC ($FF02)
+; -- Serial I/O Control (R/W)
+; --
+rSC EQU $FF02
+
+
+; --
+; -- DIV ($FF04)
+; -- Divider register (R/W)
+; --
+rDIV EQU $FF04
+
+
+; --
+; -- TIMA ($FF05)
+; -- Timer counter (R/W)
+; --
+rTIMA EQU $FF05
+
+
+; --
+; -- TMA ($FF06)
+; -- Timer modulo (R/W)
+; --
+rTMA EQU $FF06
+
+
+; --
+; -- TAC ($FF07)
+; -- Timer control (R/W)
+; --
+rTAC EQU $FF07
+
+TACF_START  EQU %00000100
+TACF_STOP   EQU %00000000
+TACF_4KHZ   EQU %00000000
+TACF_16KHZ  EQU %00000011
+TACF_65KHZ  EQU %00000010
+TACF_262KHZ EQU %00000001
+
+
+; --
+; -- IF ($FF0F)
+; -- Interrupt Flag (R/W)
+; --
+rIF EQU $FF0F
+
+
+; --
+; -- AUD1SWEEP/NR10 ($FF10)
+; -- Sweep register (R/W)
+; --
+; -- Bit 6-4 - Sweep Time
+; -- Bit 3   - Sweep Increase/Decrease
+; --           0: Addition    (frequency increases???)
+; --           1: Subtraction (frequency increases???)
+; -- Bit 2-0 - Number of sweep shift (# 0-7)
+; -- Sweep Time: (n*7.8ms)
+; --
+rNR10 EQU $FF10
+rAUD1SWEEP EQU rNR10
+
+AUD1SWEEP_UP   EQU %00000000
+AUD1SWEEP_DOWN EQU %00001000
+
+
+; --
+; -- AUD1LEN/NR11 ($FF11)
+; -- Sound length/Wave pattern duty (R/W)
+; --
+; -- Bit 7-6 - Wave Pattern Duty (00:12.5% 01:25% 10:50% 11:75%)
+; -- Bit 5-0 - Sound length data (# 0-63)
+; --
+rNR11 EQU $FF11
+rAUD1LEN EQU rNR11
+
+
+; --
+; -- AUD1ENV/NR12 ($FF12)
+; -- Envelope (R/W)
+; --
+; -- Bit 7-4 - Initial value of envelope
+; -- Bit 3   - Envelope UP/DOWN
+; --           0: Decrease
+; --           1: Range of increase
+; -- Bit 2-0 - Number of envelope sweep (# 0-7)
+; --
+rNR12 EQU $FF12
+rAUD1ENV EQU rNR12
+
+
+; --
+; -- AUD1LOW/NR13 ($FF13)
+; -- Frequency low byte (W)
+; --
+rNR13 EQU $FF13
+rAUD1LOW EQU rNR13
+
+
+; --
+; -- AUD1HIGH/NR14 ($FF14)
+; -- Frequency high byte (W)
+; --
+; -- Bit 7   - Initial (when set, sound restarts)
+; -- Bit 6   - Counter/consecutive selection
+; -- Bit 2-0 - Frequency's higher 3 bits
+; --
+rNR14 EQU $FF14
+rAUD1HIGH EQU rNR14
+
+
+; --
+; -- AUD2LEN/NR21 ($FF16)
+; -- Sound Length; Wave Pattern Duty (R/W)
+; --
+; -- see AUD1LEN for info
+; --
+rNR21 EQU $FF16
+rAUD2LEN EQU rNR21
+
+
+; --
+; -- AUD2ENV/NR22 ($FF17)
+; -- Envelope (R/W)
+; --
+; -- see AUD1ENV for info
+; --
+rNR22 EQU $FF17
+rAUD2ENV EQU rNR22
+
+
+; --
+; -- AUD2LOW/NR23 ($FF18)
+; -- Frequency low byte (W)
+; --
+rNR23 EQU $FF18
+rAUD2LOW EQU rNR23
+
+
+; --
+; -- AUD2HIGH/NR24 ($FF19)
+; -- Frequency high byte (W)
+; --
+; -- see AUD1HIGH for info
+; --
+rNR24 EQU $FF19
+rAUD2HIGH EQU rNR24
+
+
+; --
+; -- AUD3ENA/NR30 ($FF1A)
+; -- Sound on/off (R/W)
+; --
+; -- Bit 7   - Sound ON/OFF (1=ON,0=OFF)
+; --
+rNR30 EQU $FF1A
+rAUD3ENA EQU rNR30
+
+
+; --
+; -- AUD3LEN/NR31 ($FF1B)
+; -- Sound length (R/W)
+; --
+; -- Bit 7-0 - Sound length
+; --
+rNR31 EQU $FF1B
+rAUD3LEN EQU rNR31
+
+
+; --
+; -- AUD3LEVEL/NR32 ($FF1C)
+; -- Select output level
+; --
+; -- Bit 6-5 - Select output level
+; --           00: 0/1 (mute)
+; --           01: 1/1
+; --           10: 1/2
+; --           11: 1/4
+; --
+rNR32 EQU $FF1C
+rAUD3LEVEL EQU rNR32
+
+
+; --
+; -- AUD3LOW/NR33 ($FF1D)
+; -- Frequency low byte (W)
+; --
+; -- see AUD1LOW for info
+; --
+rNR33 EQU $FF1D
+rAUD3LOW EQU rNR33
+
+
+; --
+; -- AUD3HIGH/NR34 ($FF1E)
+; -- Frequency high byte (W)
+; --
+; -- see AUD1HIGH for info
+; --
+rNR34 EQU $FF1E
+rAUD3HIGH EQU rNR34
+
+
+; --
+; -- AUD4LEN/NR41 ($FF20)
+; -- Sound length (R/W)
+; --
+; -- Bit 5-0 - Sound length data (# 0-63)
+; --
+rNR41 EQU $FF20
+rAUD4LEN EQU rNR41
+
+
+; --
+; -- AUD4ENV/NR42 ($FF21)
+; -- Envelope (R/W)
+; --
+; -- see AUD1ENV for info
+; --
+rNR42 EQU $FF21
+rAUD4ENV EQU rNR42
+
+
+; --
+; -- AUD4POLY/NR43 ($FF22)
+; -- Polynomial counter (R/W)
+; --
+; -- Bit 7-4 - Selection of the shift clock frequency of the (scf)
+; --           polynomial counter (0000-1101)
+; --           freq=drf*1/2^scf (not sure)
+; -- Bit 3 -   Selection of the polynomial counter's step
+; --           0: 15 steps
+; --           1: 7 steps
+; -- Bit 2-0 - Selection of the dividing ratio of frequencies (drf)
+; --           000: f/4   001: f/8   010: f/16  011: f/24
+; --           100: f/32  101: f/40  110: f/48  111: f/56  (f=4.194304 Mhz)
+; --
+rNR43 EQU $FF22
+rAUD4POLY EQU rNR43
+
+
+; --
+; -- AUD4GO/NR44 ($FF23)
+; --
+; -- Bit 7 -   Inital
+; -- Bit 6 -   Counter/consecutive selection
+; --
+rNR44 EQU $FF23
+rAUD4GO EQU rNR44
+
+
+; --
+; -- AUDVOL/NR50 ($FF24)
+; -- Channel control / ON-OFF / Volume (R/W)
+; --
+; -- Bit 7   - Vin->SO2 ON/OFF (Vin??)
+; -- Bit 6-4 - SO2 output level (volume) (# 0-7)
+; -- Bit 3   - Vin->SO1 ON/OFF (Vin??)
+; -- Bit 2-0 - SO1 output level (volume) (# 0-7)
+; --
+rNR50 EQU $FF24
+rAUDVOL EQU rNR50
+
+AUDVOL_VIN_LEFT  EQU %10000000 ; SO2
+AUDVOL_VIN_RIGHT EQU %00001000 ; SO1
+
+
+; --
+; -- AUDTERM/NR51 ($FF25)
+; -- Selection of Sound output terminal (R/W)
+; --
+; -- Bit 7   - Output sound 4 to SO2 terminal
+; -- Bit 6   - Output sound 3 to SO2 terminal
+; -- Bit 5   - Output sound 2 to SO2 terminal
+; -- Bit 4   - Output sound 1 to SO2 terminal
+; -- Bit 3   - Output sound 4 to SO1 terminal
+; -- Bit 2   - Output sound 3 to SO1 terminal
+; -- Bit 1   - Output sound 2 to SO1 terminal
+; -- Bit 0   - Output sound 0 to SO1 terminal
+; --
+rNR51 EQU $FF25
+rAUDTERM EQU rNR51
+
+; SO2
+AUDTERM_4_LEFT  EQU %10000000
+AUDTERM_3_LEFT  EQU %01000000
+AUDTERM_2_LEFT  EQU %00100000
+AUDTERM_1_LEFT  EQU %00010000
+; SO1
+AUDTERM_4_RIGHT EQU %00001000
+AUDTERM_3_RIGHT EQU %00000100
+AUDTERM_2_RIGHT EQU %00000010
+AUDTERM_1_RIGHT EQU %00000001
+
+
+; --
+; -- AUDENA/NR52 ($FF26)
+; -- Sound on/off (R/W)
+; --
+; -- Bit 7   - All sound on/off (sets all audio regs to 0!)
+; -- Bit 3   - Sound 4 ON flag (read only)
+; -- Bit 2   - Sound 3 ON flag (read only)
+; -- Bit 1   - Sound 2 ON flag (read only)
+; -- Bit 0   - Sound 1 ON flag (read only)
+; --
+rNR52 EQU $FF26
+rAUDENA EQU rNR52
+
+AUDENA_ON    EQU %10000000
+AUDENA_OFF   EQU %00000000  ; sets all audio regs to 0!
+
+
+; --
+; -- LCDC ($FF40)
+; -- LCD Control (R/W)
+; --
+rLCDC EQU $FF40
+
+LCDCF_OFF     EQU %00000000 ; LCD Control Operation
+LCDCF_ON      EQU %10000000 ; LCD Control Operation
+LCDCF_WIN9800 EQU %00000000 ; Window Tile Map Display Select
+LCDCF_WIN9C00 EQU %01000000 ; Window Tile Map Display Select
+LCDCF_WINOFF  EQU %00000000 ; Window Display
+LCDCF_WINON   EQU %00100000 ; Window Display
+LCDCF_BG8800  EQU %00000000 ; BG & Window Tile Data Select
+LCDCF_BG8000  EQU %00010000 ; BG & Window Tile Data Select
+LCDCF_BG9800  EQU %00000000 ; BG Tile Map Display Select
+LCDCF_BG9C00  EQU %00001000 ; BG Tile Map Display Select
+LCDCF_OBJ8    EQU %00000000 ; OBJ Construction
+LCDCF_OBJ16   EQU %00000100 ; OBJ Construction
+LCDCF_OBJOFF  EQU %00000000 ; OBJ Display
+LCDCF_OBJON   EQU %00000010 ; OBJ Display
+LCDCF_BGOFF   EQU %00000000 ; BG Display
+LCDCF_BGON    EQU %00000001 ; BG Display
+; "Window Character Data Select" follows BG
+
+
+; --
+; -- STAT ($FF41)
+; -- LCDC Status   (R/W)
+; --
+rSTAT EQU $FF41
+
+STATF_LYC     EQU  %01000000 ; LYC=LY Coincidence (Selectable)
+STATF_MODE10  EQU  %00100000 ; Mode 10
+STATF_MODE01  EQU  %00010000 ; Mode 01 (V-Blank)
+STATF_MODE00  EQU  %00001000 ; Mode 00 (H-Blank)
+STATF_LYCF    EQU  %00000100 ; Coincidence Flag
+STATF_HBL     EQU  %00000000 ; H-Blank
+STATF_VBL     EQU  %00000001 ; V-Blank
+STATF_OAM     EQU  %00000010 ; OAM-RAM is used by system
+STATF_LCD     EQU  %00000011 ; Both OAM and VRAM used by system
+STATF_BUSY    EQU  %00000010 ; When set, VRAM access is unsafe
+
+
+; --
+; -- SCY ($FF42)
+; -- Scroll Y (R/W)
+; --
+rSCY EQU $FF42
+
+
+; --
+; -- SCX ($FF43)
+; -- Scroll X (R/W)
+; --
+rSCX EQU $FF43
+
+
+; --
+; -- LY ($FF44)
+; -- LCDC Y-Coordinate (R)
+; --
+; -- Values range from 0->153. 144->153 is the VBlank period.
+; --
+rLY EQU $FF44
+
+
+; --
+; -- LYC ($FF45)
+; -- LY Compare (R/W)
+; --
+; -- When LY==LYC, STATF_LYCF will be set in STAT
+; --
+rLYC EQU $FF45
+
+
+; --
+; -- DMA ($FF46)
+; -- DMA Transfer and Start Address (W)
+; --
+rDMA EQU $FF46
+
+
+; --
+; -- BGP ($FF47)
+; -- BG Palette Data (W)
+; --
+; -- Bit 7-6 - Intensity for %11
+; -- Bit 5-4 - Intensity for %10
+; -- Bit 3-2 - Intensity for %01
+; -- Bit 1-0 - Intensity for %00
+; --
+rBGP EQU $FF47
+
+
+; --
+; -- OBP0 ($FF48)
+; -- Object Palette 0 Data (W)
+; --
+; -- See BGP for info
+; --
+rOBP0 EQU $FF48
+
+
+; --
+; -- OBP1 ($FF49)
+; -- Object Palette 1 Data (W)
+; --
+; -- See BGP for info
+; --
+rOBP1 EQU $FF49
+
+
+; --
+; -- WY ($FF4A)
+; -- Window Y Position (R/W)
+; --
+; -- 0 <= WY <= 143
+; -- When WY = 0, the window is displayed from the top edge of the LCD screen.
+; --
+rWY EQU $FF4A
+
+
+; --
+; -- WX ($FF4B)
+; -- Window X Position (R/W)
+; --
+; -- 7 <= WX <= 166
+; -- When WX = 7, the window is displayed from the left edge of the LCD screen.
+; -- Values of 0-6 and 166 are unreliable due to hardware bugs.
+; --
+rWX EQU $FF4B
+
+
+; --
+; -- SPEED ($FF4D)
+; -- Select CPU Speed (R/W)
+; --
+rKEY1 EQU $FF4D
+rSPD  EQU rKEY1
+
+KEY1F_DBLSPEED EQU %10000000 ; 0=Normal Speed, 1=Double Speed (R)
+KEY1F_PREPARE  EQU %00000001 ; 0=No, 1=Prepare (R/W)
+
+
+; --
+; -- VBK ($FF4F)
+; -- Select Video RAM Bank (R/W)
+; --
+; -- Bit 0 - Bank Specification (0: Specify Bank 0; 1: Specify Bank 1)
+; --
+rVBK EQU $FF4F
+
+
+; --
+; -- HDMA1 ($FF51)
+; -- High byte for Horizontal Blanking/General Purpose DMA source address (W)
+; -- CGB Mode Only
+; --
+rHDMA1 EQU $FF51
+
+
+; --
+; -- HDMA2 ($FF52)
+; -- Low byte for Horizontal Blanking/General Purpose DMA source address (W)
+; -- CGB Mode Only
+; --
+rHDMA2 EQU $FF52
+
+
+; --
+; -- HDMA3 ($FF53)
+; -- High byte for Horizontal Blanking/General Purpose DMA destination address (W)
+; -- CGB Mode Only
+; --
+rHDMA3 EQU $FF53
+
+
+; --
+; -- HDMA4 ($FF54)
+; -- Low byte for Horizontal Blanking/General Purpose DMA destination address (W)
+; -- CGB Mode Only
+; --
+rHDMA4 EQU $FF54
+
+
+; --
+; -- HDMA5 ($FF55)
+; -- Transfer length (in tiles minus 1)/mode/start for Horizontal Blanking, General Purpose DMA (R/W)
+; -- CGB Mode Only
+; --
+rHDMA5 EQU $FF55
+
+HDMA5F_MODE_GP  EQU %00000000 ; General Purpose DMA (W)
+HDMA5F_MODE_HBL EQU %10000000 ; HBlank DMA (W)
+
+; -- Once DMA has started, use HDMA5F_BUSY to check when the transfer is complete
+HDMA5F_BUSY EQU %10000000 ; 0=Busy (DMA still in progress), 1=Transfer complete (R)
+
+
+; --
+; -- RP ($FF56)
+; -- Infrared Communications Port (R/W)
+; -- CGB Mode Only
+; --
+rRP EQU $FF56
+
+RPF_ENREAD   EQU %11000000
+RPF_DATAIN   EQU %00000010 ; 0=Receiving IR Signal, 1=Normal
+RPF_WRITE_HI EQU %00000001
+RPF_WRITE_LO EQU %00000000
+
+
+; --
+; -- BCPS ($FF68)
+; -- Background Color Palette Specification (R/W)
+; --
+rBCPS EQU $FF68
+
+BCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
+
+
+; --
+; -- BCPD ($FF69)
+; -- Background Color Palette Data (R/W)
+; --
+rBCPD EQU $FF69
+
+
+; --
+; -- OCPS ($FF6A)
+; -- Object Color Palette Specification (R/W)
+; --
+rOCPS EQU $FF6A
+
+OCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
+
+
+; --
+; -- OCPD ($FF6B)
+; -- Object Color Palette Data (R/W)
+; --
+rOCPD EQU $FF6B
+
+
+; --
+; -- SMBK/SVBK ($FF70)
+; -- Select Main RAM Bank (R/W)
+; --
+; -- Bit 2-0 - Bank Specification (0,1: Specify Bank 1; 2-7: Specify Banks 2-7)
+; --
+rSVBK EQU $FF70
+rSMBK EQU rSVBK
+
+
+; --
+; -- PCM12 ($FF76)
+; -- Sound channel 1&2 PCM amplitude (R)
+; --
+; -- Bit 7-4 - Copy of sound channel 2's PCM amplitude
+; -- Bit 3-0 - Copy of sound channel 1's PCM amplitude
+; --
+rPCM12 EQU $FF76
+
+
+; --
+; -- PCM34 ($FF77)
+; -- Sound channel 3&4 PCM amplitude (R)
+; --
+; -- Bit 7-4 - Copy of sound channel 4's PCM amplitude
+; -- Bit 3-0 - Copy of sound channel 3's PCM amplitude
+; --
+rPCM34 EQU $FF77
+
+
+; --
+; -- IE ($FFFF)
+; -- Interrupt Enable (R/W)
+; --
+rIE EQU $FFFF
+
+IEF_HILO   EQU %00010000 ; Transition from High to Low of Pin number P10-P13
+IEF_SERIAL EQU %00001000 ; Serial I/O transfer end
+IEF_TIMER  EQU %00000100 ; Timer Overflow
+IEF_LCDC   EQU %00000010 ; LCDC (see STAT)
+IEF_VBLANK EQU %00000001 ; V-Blank
+
+
+;***************************************************************************
+;*
+;* Flags common to multiple sound channels
+;*
+;***************************************************************************
+
+; --
+; -- Square wave duty cycle
+; --
+; -- Can be used with AUD1LEN and AUD2LEN
+; -- See AUD1LEN for more info
+; --
+AUDLEN_DUTY_12_5    EQU %00000000 ; 12.5%
+AUDLEN_DUTY_25      EQU %01000000 ; 25%
+AUDLEN_DUTY_50      EQU %10000000 ; 50%
+AUDLEN_DUTY_75      EQU %11000000 ; 75%
+
+
+; --
+; -- Audio envelope flags
+; --
+; -- Can be used with AUD1ENV, AUD2ENV, AUD4ENV
+; -- See AUD1ENV for more info
+; --
+AUDENV_UP           EQU %00001000
+AUDENV_DOWN         EQU %00000000
+
+
+; --
+; -- Audio trigger flags
+; --
+; -- Can be used with AUD1HIGH, AUD2HIGH, AUD3HIGH
+; -- See AUD1HIGH for more info
+; --
+
+AUDHIGH_RESTART     EQU %10000000
+AUDHIGH_LENGTH_ON   EQU %01000000
+AUDHIGH_LENGTH_OFF  EQU %00000000
+
+
+;***************************************************************************
+;*
+;* CPU values on bootup (a=type, b=qualifier)
+;*
+;***************************************************************************
+
+BOOTUP_A_DMG    EQU $01 ; Dot Matrix Game
+BOOTUP_A_CGB    EQU $11 ; Color GameBoy
+BOOTUP_A_MGB    EQU $FF ; Mini GameBoy (Pocket GameBoy)
+
+; if a=BOOTUP_A_CGB, bit 0 in b can be checked to determine if real CGB or
+; other system running in GBC mode
+BOOTUP_B_CGB    EQU %00000000
+BOOTUP_B_AGB    EQU %00000001   ; GBA, GBA SP, Game Boy Player, or New GBA SP
+
+
+;***************************************************************************
+;*
+;* Cart related
+;*
+;***************************************************************************
+
+; $0143 Color GameBoy compatibility code
+CART_COMPATIBLE_DMG     EQU $00
+CART_COMPATIBLE_DMG_GBC EQU $80
+CART_COMPATIBLE_GBC     EQU $C0
+
+; $0146 GameBoy/Super GameBoy indicator
+CART_INDICATOR_GB       EQU $00
+CART_INDICATOR_SGB      EQU $03
+
+; $0147 Cartridge type
+CART_ROM                     EQU $00
+CART_ROM_MBC1                EQU $01
+CART_ROM_MBC1_RAM            EQU $02
+CART_ROM_MBC1_RAM_BAT        EQU $03
+CART_ROM_MBC2                EQU $05
+CART_ROM_MBC2_BAT            EQU $06
+CART_ROM_RAM                 EQU $08
+CART_ROM_RAM_BAT             EQU $09
+CART_ROM_MMM01               EQU $0B
+CART_ROM_MMM01_RAM           EQU $0C
+CART_ROM_MMM01_RAM_BAT       EQU $0D
+CART_ROM_MBC3_BAT_RTC        EQU $0F
+CART_ROM_MBC3_RAM_BAT_RTC    EQU $10
+CART_ROM_MBC3                EQU $11
+CART_ROM_MBC3_RAM            EQU $12
+CART_ROM_MBC3_RAM_BAT        EQU $13
+CART_ROM_MBC5                EQU $19
+CART_ROM_MBC5_BAT            EQU $1A
+CART_ROM_MBC5_RAM_BAT        EQU $1B
+CART_ROM_MBC5_RUMBLE         EQU $1C
+CART_ROM_MBC5_RAM_RUMBLE     EQU $1D
+CART_ROM_MBC5_RAM_BAT_RUMBLE EQU $1E
+CART_ROM_MBC7_RAM_BAT_GYRO   EQU $22
+CART_ROM_POCKET_CAMERA       EQU $FC
+CART_ROM_BANDAI_TAMA5        EQU $FD
+CART_ROM_HUDSON_HUC3         EQU $FE
+CART_ROM_HUDSON_HUC1         EQU $FF
+
+; $0148 ROM size
+; these are kilobytes
+CART_ROM_32KB   EQU $00 ; 2 banks
+CART_ROM_64KB   EQU $01 ; 4 banks
+CART_ROM_128KB  EQU $02 ; 8 banks
+CART_ROM_256KB  EQU $03 ; 16 banks
+CART_ROM_512KB  EQU $04 ; 32 banks
+CART_ROM_1024KB EQU $05 ; 64 banks
+CART_ROM_2048KB EQU $06 ; 128 banks
+CART_ROM_4096KB EQU $07 ; 256 banks
+CART_ROM_8192KB EQU $08 ; 512 banks
+CART_ROM_1152KB EQU $52 ; 72 banks
+CART_ROM_1280KB EQU $53 ; 80 banks
+CART_ROM_1536KB EQU $54 ; 96 banks
+
+; $0149 SRAM size
+; these are kilobytes
+CART_SRAM_NONE  EQU 0
+CART_SRAM_2KB   EQU 1 ; 1 incomplete bank
+CART_SRAM_8KB   EQU 2 ; 1 bank
+CART_SRAM_32KB  EQU 3 ; 4 banks
+CART_SRAM_128KB EQU 4 ; 16 banks
+
+CART_SRAM_ENABLE  EQU $0A
+CART_SRAM_DISABLE EQU $00
+
+; $014A Destination code
+CART_DEST_JAPANESE     EQU $00
+CART_DEST_NON_JAPANESE EQU $01
+
+
+;***************************************************************************
+;*
+;* Keypad related
+;*
+;***************************************************************************
+
+PADF_DOWN   EQU $80
+PADF_UP     EQU $40
+PADF_LEFT   EQU $20
+PADF_RIGHT  EQU $10
+PADF_START  EQU $08
+PADF_SELECT EQU $04
+PADF_B      EQU $02
+PADF_A      EQU $01
+
+PADB_DOWN   EQU $7
+PADB_UP     EQU $6
+PADB_LEFT   EQU $5
+PADB_RIGHT  EQU $4
+PADB_START  EQU $3
+PADB_SELECT EQU $2
+PADB_B      EQU $1
+PADB_A      EQU $0
+
+
+;***************************************************************************
+;*
+;* Screen related
+;*
+;***************************************************************************
+
+SCRN_X    EQU 160 ; Width of screen in pixels
+SCRN_Y    EQU 144 ; Height of screen in pixels
+SCRN_X_B  EQU 20  ; Width of screen in bytes
+SCRN_Y_B  EQU 18  ; Height of screen in bytes
+
+SCRN_VX   EQU 256 ; Virtual width of screen in pixels
+SCRN_VY   EQU 256 ; Virtual height of screen in pixels
+SCRN_VX_B EQU 32  ; Virtual width of screen in bytes
+SCRN_VY_B EQU 32  ; Virtual height of screen in bytes
+
+
+;***************************************************************************
+;*
+;* OAM related
+;*
+;***************************************************************************
+
+; OAM attributes
+; each entry in OAM RAM is 4 bytes (sizeof_OAM_ATTRS)
+RSRESET
+OAMA_Y              RB  1   ; y pos
+OAMA_X              RB  1   ; x pos
+OAMA_TILEID         RB  1   ; tile id
+OAMA_FLAGS          RB  1   ; flags (see below)
+sizeof_OAM_ATTRS    RB  0
+
+OAM_COUNT           EQU 40  ; number of OAM entries in OAM RAM
+
+; flags
+OAMF_PRI        EQU %10000000 ; Priority
+OAMF_YFLIP      EQU %01000000 ; Y flip
+OAMF_XFLIP      EQU %00100000 ; X flip
+OAMF_PAL0       EQU %00000000 ; Palette number; 0,1 (DMG)
+OAMF_PAL1       EQU %00010000 ; Palette number; 0,1 (DMG)
+OAMF_BANK0      EQU %00000000 ; Bank number; 0,1 (GBC)
+OAMF_BANK1      EQU %00001000 ; Bank number; 0,1 (GBC)
+
+OAMF_PALMASK    EQU %00000111 ; Palette (GBC)
+
+OAMB_PRI        EQU 7 ; Priority
+OAMB_YFLIP      EQU 6 ; Y flip
+OAMB_XFLIP      EQU 5 ; X flip
+OAMB_PAL1       EQU 4 ; Palette number; 0,1 (DMG)
+OAMB_BANK1      EQU 3 ; Bank number; 0,1 (GBC)
+
+
+;*
+;* Nintendo scrolling logo
+;* (Code won't work on a real GameBoy)
+;* (if next lines are altered.)
+NINTENDO_LOGO : MACRO
+    DB  $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D
+    DB  $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99
+    DB  $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E
+ENDM
+
+    ENDC ;HARDWARE_INC
diff --git a/code/main.asm b/code/main.asm
new file mode 100644
index 0000000..613a19d
--- /dev/null
+++ b/code/main.asm
@@ -0,0 +1,731 @@
+include "hardware.inc"
+include "constants.inc"
+include "signals.asm"
+include "ops.asm"
+include "tick.asm"
+
+; --------------------------------------------------------------------------------------------------------------------
+; Interrupt Vectors
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "Vblank", ROM0[$0040]
+  jp UpdateTiles
+
+SECTION "LCDC",   ROM0[$0048]
+  reti
+
+SECTION "Timer",  ROM0[$0050]
+  jp Timer
+
+SECTION "Serial", ROM0[$0058]
+  reti
+
+SECTION "Joypad", ROM0[$0060]
+  reti
+
+; Entry point
+SECTION "Entry",  ROM0[$100]
+  nop
+  jp start
+
+; --------------------------------------------------------------------------------------------------------------------
+; Header
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "Header",ROM0[$0104]
+
+    ; Logo
+    DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D
+    DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99
+    DB $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E
+
+    ; ROM Details
+    DB "8BIT00000000000" ; $134 - Title (exactly 15 characters)
+    DB   0                ; $143 - GBC Functionality: No
+    DB   0,0              ; $144 - Licensee code
+    DB   0                ; $146 - SGB Support: No
+    DB   0                ; $147 - Cart type: No MBC (32K ROM only)
+    DB   0                ; $148 - ROM Size: 32K (No Banking)
+    DB   0                ; $149 - External ram Size: None
+    DB   1                ; $14a - Destination: Non-Japan
+    DB   $33              ; $14b - Old Licensee code: must be $33
+    DB   0                ; $14c - Mask ROM version
+    DB   0                ; $14d - Complement check (RGBDS will fill)
+    DW   0                ; $14e - Checksum (RGBDS will fill)
+
+; --------------------------------------------------------------------------------------------------------------------
+; Entry Point
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "Main", ROM0[$150]
+start:
+  di
+  ld SP, $FFFF
+
+; Turn LCD off
+.wait_for_vblank
+  ldh a, [rLY]
+  cp 145
+  jr nz, .wait_for_vblank
+  ld a, [rLCDC]
+  xor LCDCF_ON
+  ld [rLCDC], a
+
+  ; Load tiles into VRAM
+  ld hl, _VRAM
+  ld de, Tiles_Begin
+  ld bc, Tiles_End-Tiles_Begin
+  call CopyBytes
+
+  ; Fill the map
+  ld hl, _SCRN0
+  ld de, TileMap_Begin
+  ld bc, TileMap_End-TileMap_Begin
+  call CopyBytes
+
+  ; Set background palette
+  ld a, %11100100
+  ld [rBGP], a
+
+  ; Turn LCD back on
+  ld a, [rLCDC]
+  or LCDCF_ON
+  ld [rLCDC], a
+
+  ; Set up timer and vblank interrupts
+  ld a, IEF_TIMER | IEF_VBLANK
+  ld [rIE], a
+
+  ; Configure timer
+  ; TODO: Make this adjustable at runtime (clock speed adjust)
+  ld a, TACF_4KHZ | TACF_START
+  ld [rTAC], a
+  xor a
+  ld [rTMA], a
+
+  ; Zero all state
+  ld hl, StateBegin
+  ld bc, StateEnd-StateBegin
+  call SetByte
+
+  ; Zero all values
+  ld hl, DataBegin
+  ld bc, DataEnd-DataBegin
+  call SetByte
+
+  ; Turn off all LEDs
+  ld a, LED_OFF
+  ld hl, LedBegin
+  ld bc, LedEnd-LedBegin
+  call SetByte
+
+  ; Load the program
+  ; TODO: Make this programmable at runtime
+  ld a, $e0
+  ld [ram], a    ; OUT
+  ld a, $2f
+  ld [ram+1], a  ; ADD 15
+  ld a, $74
+  ld [ram+2], a  ; JC 4
+  ld a, $60
+  ld [ram+3], a  ; JMP 0
+  ld a, $3f
+  ld [ram+4], a  ; SUB 15
+  ld a, $e0
+  ld [ram+5], a  ; OUT
+  ld a, $80
+  ld [ram+6], a  ; JZ 0
+  ld a, $64
+  ld [ram+7], a  ; JMP 4
+  xor a
+  ld [ram+8], a  ; NOP
+  ld [ram+9], a  ; NOP
+  ld [ram+10], a ; NOP
+  ld [ram+11], a ; NOP
+  ld [ram+12], a ; NOP
+  ld [ram+13], a ; NOP
+  ld [ram+14], a ; NOP
+  ld a, 15
+  ld [ram+15], a ; Data
+
+  ; Load default clock of 1Hz (16 timer interrupts)
+  ld a, 2
+  ld [clk], a
+  ld a, 1
+  ld [clk_div2], a
+
+  ; Initialize as running
+  ld a, 1
+  ld [running], a
+
+  ; Tick once before we begin to set the stage
+  call Tick
+
+  ei
+
+.loop
+  halt
+  nop
+
+  ; If we aren't running, loop
+  ld a, [running]
+  cp 1
+  jr nz, .loop
+
+  ; Check for Button A state
+  ; State is only set once per press; no repeats
+  call ReadKeys
+  bit 0, a
+  jr z, .key_released
+
+.key_pressed:
+  ld a, LED_ON
+  ld [clk_led], a
+  ld a, [button_state]
+  cp 0
+  jr z, .tick
+  jr .loop
+
+.key_released:
+  xor a
+  ld [button_state], a
+  ld a, LED_OFF
+  ld [clk_led], a
+  jr .loop
+
+.tick:
+  ; Key press = rising edge
+  ; Key release = falling edge
+  ld a, 1
+  ld [button_state], a
+  call Tick
+  jr .loop
+
+
+; [in] de: Source address
+; [in] hl: Destination address
+; [in] bc: Count
+CopyBytes:
+  ; Increment each by one to prevent rolling over when decrementing
+  inc b
+  inc c
+  jr .skip
+
+.loop:
+  ld a, [de]
+  ld [hl+], a
+  inc de
+
+.skip:
+  dec c
+  jr nz, .loop
+  dec b
+  jr nz, .loop
+
+  ret
+
+
+; [in] a: Byte to set
+; [in] hl: Destination address
+; [in] bc: Count
+SetByte:
+  ; Increment each by one to prevent rolling over when decrementing
+  inc b
+  inc c
+  jr .skip
+
+.loop
+  ld [hl+], a
+
+.skip:
+  dec c
+  jr nz, .loop
+  dec b
+  jr nz, .loop
+  ret
+
+; [out] a: x x x x start select b a
+ReadKeys:
+  ld	a, P1F_GET_BTN ;
+  ld	[rP1], a ; joypad info
+  ld	a, [rP1] ;
+  ld	a, [rP1] ; read twice to make sure
+  and	$0f	     ; low nibble contains buttons
+  cpl		     ; low means pressed so we complement for logic purposes
+  ret
+
+
+SECTION "Handlers", ROM0
+Timer:
+  push af
+
+  ld a, [w_counter]
+  add a, 1
+  ld [w_counter], a
+  ld hl, clk_div2
+  cp [hl]
+  jr z, .rising_edge
+  ld hl, clk
+  cp [hl]
+  jr z, .falling_edge
+  jr .exit
+
+.rising_edge:
+  ld a, LED_ON
+  ld [clk_led], a
+  call Tick
+  jr .exit
+
+.falling_edge:
+  ld a, LED_OFF
+  ld [clk_led], a
+  xor a
+  ld [w_counter], a
+
+.exit:
+  pop af
+  reti
+
+UpdateTiles:
+  push af
+
+  ; CLK
+  ld hl, _SCRN0 + 4
+  ld a, [clk_led]
+  ld [hl], a
+
+  ; PC
+  ld hl, _SCRN0 + 13
+  ld a, [pc_led_3]
+  ld [hl+], a
+  ld a, [pc_led_2]
+  ld [hl+], a
+  ld a, [pc_led_1]
+  ld [hl+], a
+  ld a, [pc_led_0]
+  ld [hl], a
+
+  ; OP
+  ld hl, _SCRN0 + $040 + 14
+  ld a, [opc_led_2]
+  ld [hl+], a
+  ld a, [opc_led_1]
+  ld [hl+], a
+  ld a, [opc_led_0]
+  ld [hl], a
+
+  ; IR
+  ld hl, _SCRN0 + $040 + 4
+  ld a, [ir_led_7]
+  ld [hl+], a
+  ld a, [ir_led_6]
+  ld [hl+], a
+  ld a, [ir_led_5]
+  ld [hl+], a
+  ld a, [ir_led_4]
+  ld [hl+], a
+  ld a, [ir_led_3]
+  ld [hl+], a
+  ld a, [ir_led_2]
+  ld [hl+], a
+  ld a, [ir_led_1]
+  ld [hl+], a
+  ld a, [ir_led_0]
+  ld [hl], a
+
+  ; MAR
+  ld hl, _SCRN0 + $080 + 4
+  ld a, [mar_led_3]
+  ld [hl+], a
+  ld a, [mar_led_2]
+  ld [hl+], a
+  ld a, [mar_led_1]
+  ld [hl+], a
+  ld a, [mar_led_0]
+  ld [hl], a
+
+  ; BUS
+  ld hl, _SCRN0 + $0A0 + 4
+  ld a, [mem_led_7]
+  ld [hl+], a
+  ld a, [mem_led_6]
+  ld [hl+], a
+  ld a, [mem_led_5]
+  ld [hl+], a
+  ld a, [mem_led_4]
+  ld [hl+], a
+  ld a, [mem_led_3]
+  ld [hl+], a
+  ld a, [mem_led_2]
+  ld [hl+], a
+  ld a, [mem_led_1]
+  ld [hl+], a
+  ld a, [mem_led_0]
+  ld [hl], a
+
+  ; BUS
+  ld hl, _SCRN0 + $0E0 + 4
+  ld a, [bus_led_7]
+  ld [hl+], a
+  ld a, [bus_led_6]
+  ld [hl+], a
+  ld a, [bus_led_5]
+  ld [hl+], a
+  ld a, [bus_led_4]
+  ld [hl+], a
+  ld a, [bus_led_3]
+  ld [hl+], a
+  ld a, [bus_led_2]
+  ld [hl+], a
+  ld a, [bus_led_1]
+  ld [hl+], a
+  ld a, [bus_led_0]
+  ld [hl], a
+
+  ; A
+  ld hl, _SCRN0 + $120 + 4
+  ld a, [a_led_7]
+  ld [hl+], a
+  ld a, [a_led_6]
+  ld [hl+], a
+  ld a, [a_led_5]
+  ld [hl+], a
+  ld a, [a_led_4]
+  ld [hl+], a
+  ld a, [a_led_3]
+  ld [hl+], a
+  ld a, [a_led_2]
+  ld [hl+], a
+  ld a, [a_led_1]
+  ld [hl+], a
+  ld a, [a_led_0]
+  ld [hl], a
+
+  ; B
+  ld hl, _SCRN0 + $140 + 4
+  ld a, [b_led_7]
+  ld [hl+], a
+  ld a, [b_led_6]
+  ld [hl+], a
+  ld a, [b_led_5]
+  ld [hl+], a
+  ld a, [b_led_4]
+  ld [hl+], a
+  ld a, [b_led_3]
+  ld [hl+], a
+  ld a, [b_led_2]
+  ld [hl+], a
+  ld a, [b_led_1]
+  ld [hl+], a
+  ld a, [b_led_0]
+  ld [hl], a
+
+  ; ALU
+  ld hl, _SCRN0 + $160 + 4
+  ld a, [alu_led_7]
+  ld [hl+], a
+  ld a, [alu_led_6]
+  ld [hl+], a
+  ld a, [alu_led_5]
+  ld [hl+], a
+  ld a, [alu_led_4]
+  ld [hl+], a
+  ld a, [alu_led_3]
+  ld [hl+], a
+  ld a, [alu_led_2]
+  ld [hl+], a
+  ld a, [alu_led_1]
+  ld [hl+], a
+  ld a, [alu_led_0]
+  ld [hl], a
+
+  ; CTRL
+  ld hl, _SCRN0 + $1A0 + 4
+  ld a, [ctrl_led_ht]
+  ld [hl+], a
+  ld a, [ctrl_led_mi]
+  ld [hl+], a
+  ld a, [ctrl_led_ri]
+  ld [hl+], a
+  ld a, [ctrl_led_ro]
+  ld [hl+], a
+  ld a, [ctrl_led_io]
+  ld [hl+], a
+  ld a, [ctrl_led_ii]
+  ld [hl+], a
+  ld a, [ctrl_led_ai]
+  ld [hl+], a
+  ld a, [ctrl_led_ao]
+  ld [hl+], a
+  ld a, [ctrl_led_eo]
+  ld [hl+], a
+  ld a, [ctrl_led_su]
+  ld [hl+], a
+  ld a, [ctrl_led_bi]
+  ld [hl+], a
+  ld a, [ctrl_led_oi]
+  ld [hl+], a
+  ld a, [ctrl_led_ce]
+  ld [hl+], a
+  ld a, [ctrl_led_co]
+  ld [hl+], a
+  ld a, [ctrl_led_jp]
+  ld [hl+], a
+  ld a, [ctrl_led_fi]
+  ld [hl], a
+
+  ; Flags
+  ld hl, _SCRN0 + $160 + 13
+  ld a, [flag_led_c]
+  ld [hl+], a
+  ld a, [flag_led_z]
+  ld [hl], a
+
+  ; OUT
+  ld hl, _SCRN0 +  $220 + 4
+  ; 100s
+  ld a, [display]
+  add a, $1 ; $1 = tile id of 0
+  ld [hl+], a
+  ; 10s
+  ld a, [display+1]
+  add a, $1
+  ld [hl+], a
+  ; 1s
+  ld a, [display+2]
+  add a, $1
+  ld [hl], a
+
+.exit
+  pop af
+  reti
+
+
+; --------------------------------------------------------------------------------------------------------------------
+; Tile Data
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "Tile Data", ROM0
+
+Tiles_Begin:
+DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF ; Blank   ($00)
+DB $83,$83,$7D,$7D,$6D,$6D,$6D,$6D,$6D,$6D,$7D,$7D,$83,$83,$FF,$FF ; 0       ($01)
+DB $EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$FF,$FF ; 1       ($02)
+DB $07,$07,$FB,$FB,$FB,$FB,$87,$87,$7F,$7F,$7F,$7F,$03,$03,$FF,$FF ; 2       ($03)
+DB $03,$03,$FD,$FD,$FD,$FD,$83,$83,$FD,$FD,$FD,$FD,$03,$03,$FF,$FF ; 3       ($04)
+DB $7D,$7D,$7D,$7D,$7D,$7D,$81,$81,$FD,$FD,$FD,$FD,$FD,$FD,$FF,$FF ; 4       ($05)
+DB $03,$03,$7F,$7F,$7F,$7F,$07,$07,$FB,$FB,$FB,$FB,$07,$07,$FF,$FF ; 5       ($06)
+DB $83,$83,$7F,$7F,$7F,$7F,$03,$03,$7D,$7D,$7D,$7D,$83,$83,$FF,$FF ; 6       ($07)
+DB $01,$01,$FD,$FD,$FD,$FD,$FD,$FD,$FD,$FD,$FD,$FD,$FD,$FD,$FF,$FF ; 7       ($08)
+DB $83,$83,$7D,$7D,$7D,$7D,$83,$83,$7D,$7D,$7D,$7D,$83,$83,$FF,$FF ; 8       ($09)
+DB $83,$83,$7D,$7D,$7D,$7D,$81,$81,$FD,$FD,$FD,$FD,$FD,$FD,$FF,$FF ; 9       ($0A)
+DB $C7,$C7,$BB,$BB,$7D,$7D,$7D,$7D,$01,$01,$7D,$7D,$7D,$7D,$FF,$FF ; A       ($0B)
+DB $03,$03,$7D,$7D,$7D,$7D,$03,$03,$7D,$7D,$7D,$7D,$03,$03,$FF,$FF ; B       ($0C)
+DB $83,$83,$7D,$7D,$7F,$7F,$7F,$7F,$7F,$7F,$7D,$7D,$83,$83,$FF,$FF ; C       ($0D)
+DB $03,$03,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$03,$03,$FF,$FF ; D       ($0E)
+DB $83,$83,$7F,$7F,$7F,$7F,$07,$07,$7F,$7F,$7F,$7F,$83,$83,$FF,$FF ; E       ($0F)
+DB $01,$01,$7F,$7F,$7F,$7F,$03,$03,$7F,$7F,$7F,$7F,$7F,$7F,$FF,$FF ; F       ($10)
+DB $83,$83,$7D,$7D,$7F,$7F,$61,$61,$7D,$7D,$7D,$7D,$83,$83,$FF,$FF ; G       ($11)
+DB $7D,$7D,$7D,$7D,$7D,$7D,$01,$01,$7D,$7D,$7D,$7D,$7D,$7D,$FF,$FF ; H       ($12)
+DB $01,$01,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$01,$01,$FF,$FF ; I       ($13)
+DB $01,$01,$F7,$F7,$F7,$F7,$F7,$F7,$77,$77,$77,$77,$8F,$8F,$FF,$FF ; J       ($14)
+DB $7B,$7B,$7B,$7B,$7B,$7B,$07,$07,$7B,$7B,$7B,$7B,$7B,$7B,$FF,$FF ; K       ($15)
+DB $7F,$7F,$7F,$7F,$7F,$7F,$7F,$7F,$7F,$7F,$7F,$7F,$03,$03,$FF,$FF ; L       ($16)
+DB $BB,$BB,$55,$55,$6D,$6D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$FF,$FF ; M       ($17)
+DB $03,$03,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$FF,$FF ; N       ($18)
+DB $83,$83,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$83,$83,$FF,$FF ; O       ($19)
+DB $03,$03,$7D,$7D,$7D,$7D,$03,$03,$7F,$7F,$7F,$7F,$7F,$7F,$FF,$FF ; P       ($1A)
+DB $83,$83,$7D,$7D,$7D,$7D,$7D,$7D,$75,$75,$7B,$7B,$85,$85,$FF,$FF ; Q       ($1B)
+DB $83,$83,$7D,$7D,$7D,$7D,$03,$03,$7D,$7D,$7D,$7D,$7D,$7D,$FF,$FF ; R       ($1C)
+DB $81,$81,$7F,$7F,$7F,$7F,$83,$83,$FD,$FD,$FD,$FD,$03,$03,$FF,$FF ; S       ($1D)
+DB $01,$01,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$EF,$FF,$FF ; T       ($1E)
+DB $7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$83,$83,$FF,$FF ; U       ($1F)
+DB $7D,$7D,$7D,$7D,$BB,$BB,$BB,$BB,$D7,$D7,$D7,$D7,$EF,$EF,$FF,$FF ; V       ($20)
+DB $7D,$7D,$7D,$7D,$7D,$7D,$7D,$7D,$6D,$6D,$55,$55,$BB,$BB,$FF,$FF ; W       ($21)
+DB $7D,$7D,$BB,$BB,$D7,$D7,$EF,$EF,$D7,$D7,$BB,$BB,$7D,$7D,$FF,$FF ; X       ($22)
+DB $7D,$7D,$7D,$7D,$BB,$BB,$D7,$D7,$EF,$EF,$EF,$EF,$EF,$EF,$FF,$FF ; Y       ($23)
+DB $01,$01,$FD,$FD,$FB,$FB,$C7,$C7,$BF,$BF,$7F,$7F,$01,$01,$FF,$FF ; Z       ($24)
+DB $FF,$83,$83,$7D,$83,$7D,$83,$7D,$83,$7D,$83,$7D,$FF,$83,$FF,$FF ; LED Off ($25)
+DB $FF,$83,$83,$01,$83,$01,$83,$01,$83,$01,$83,$01,$FF,$83,$FF,$FF ; LED On  ($26)
+Tiles_End:
+
+; --------------------------------------------------------------------------------------------------------------------
+; Tile Map
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "Tile Map", ROM0
+
+TileMap_Begin:
+DB $0D,$16,$15,$00,$25,$00,$00,$00,$00,$00,$00,$00,$00,$25,$25,$25,$25,$00,$1A,$0D,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$000] CLK  PC
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$020]
+DB $00,$13,$1C,$00,$25,$25,$25,$25,$25,$25,$25,$25,$00,$00,$25,$25,$25,$00,$19,$1A,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$040] IR   OP
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$060]
+DB $17,$0B,$1C,$00,$25,$25,$25,$25,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$080] MAR
+DB $17,$0F,$17,$00,$25,$25,$25,$25,$25,$25,$25,$25,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$0A0] MEM
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$0C0]
+DB $0C,$1F,$1D,$00,$25,$25,$25,$25,$25,$25,$25,$25,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$0E0] BUS
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$100]
+DB $00,$00,$0B,$00,$25,$25,$25,$25,$25,$25,$25,$25,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$120] A
+DB $00,$00,$0C,$00,$25,$25,$25,$25,$25,$25,$25,$25,$00,$0D,$24,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$140] B    C Z
+DB $0B,$16,$1F,$00,$25,$25,$25,$25,$25,$25,$25,$25,$00,$25,$25,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$160] ALU  x x
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$080]
+DB $0D,$1E,$16,$00,$25,$25,$25,$25,$25,$25,$25,$25,$25,$25,$25,$25,$25,$25,$25,$25,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$1A0] CTL
+DB $00,$00,$00,$00,$12,$17,$1C,$1C,$13,$13,$0B,$0B,$0F,$1D,$0C,$19,$0D,$0D,$14,$10,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$1C0] H M R R I I A A E S B O C C J F
+DB $00,$00,$00,$00,$1E,$13,$13,$19,$19,$13,$13,$19,$19,$1F,$13,$13,$0F,$19,$1A,$13,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$1E0] T I I O O I I O O U I I E O P I
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$200]
+DB $19,$1F,$1E,$00,$01,$01,$01,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00 ; [$220] OUT
+
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+DB $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,  $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+TileMap_End:
+
+
+; --------------------------------------------------------------------------------------------------------------------
+; State
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "State", WRAM0
+
+StateBegin:
+
+w_counter: DS 1
+clk: DS 1
+clk_div2: DS 1
+button_state: DS 1
+running: DS 1
+flags_temp: DS 1
+
+StateEnd:
+
+; --------------------------------------------------------------------------------------------------------------------
+; Data
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "Data", WRAM0
+
+DataBegin:
+
+bus:     DS 1 ; 8 bit
+mar:     DS 1 ; 4 bit
+mem:     DS 1 ; 8 bit
+ir:      DS 1 ; 8 bit
+pc:      DS 1 ; 4 bit
+opc:     DS 1 ; 3 bit
+a_reg:   DS 1 ; 8 bit
+b_reg:   DS 1 ; 8 bit
+alu:     DS 1 ; 8 bit
+out_reg: DS 1 ; 8 bit
+ctrl:    DS 2 ; ht | mi | ri | ro | io | ii | ai | ao || eo | su | bi | oi | ce | co | jp | fi
+flags:   DS 1 ; c | z
+ram:     DS 16
+
+DataEnd:
+
+; --------------------------------------------------------------------------------------------------------------------
+; LEDs
+; --------------------------------------------------------------------------------------------------------------------
+SECTION "LEDs", WRAM0
+
+LedBegin:
+
+clk_led: DS 1
+
+bus_led_7: DS 1
+bus_led_6: DS 1
+bus_led_5: DS 1
+bus_led_4: DS 1
+bus_led_3: DS 1
+bus_led_2: DS 1
+bus_led_1: DS 1
+bus_led_0: DS 1
+
+mar_led_3: DS 1
+mar_led_2: DS 1
+mar_led_1: DS 1
+mar_led_0: DS 1
+
+mem_led_7: DS 1
+mem_led_6: DS 1
+mem_led_5: DS 1
+mem_led_4: DS 1
+mem_led_3: DS 1
+mem_led_2: DS 1
+mem_led_1: DS 1
+mem_led_0: DS 1
+
+opc_led_2: DS 1
+opc_led_1: DS 1
+opc_led_0: DS 1
+
+pc_led_3: DS 1
+pc_led_2: DS 1
+pc_led_1: DS 1
+pc_led_0: DS 1
+
+ir_led_7: DS 1
+ir_led_6: DS 1
+ir_led_5: DS 1
+ir_led_4: DS 1
+ir_led_3: DS 1
+ir_led_2: DS 1
+ir_led_1: DS 1
+ir_led_0: DS 1
+
+a_led_7: DS 1
+a_led_6: DS 1
+a_led_5: DS 1
+a_led_4: DS 1
+a_led_3: DS 1
+a_led_2: DS 1
+a_led_1: DS 1
+a_led_0: DS 1
+
+b_led_7: DS 1
+b_led_6: DS 1
+b_led_5: DS 1
+b_led_4: DS 1
+b_led_3: DS 1
+b_led_2: DS 1
+b_led_1: DS 1
+b_led_0: DS 1
+
+alu_led_7: DS 1
+alu_led_6: DS 1
+alu_led_5: DS 1
+alu_led_4: DS 1
+alu_led_3: DS 1
+alu_led_2: DS 1
+alu_led_1: DS 1
+alu_led_0: DS 1
+
+ctrl_led_ht: DS 1
+ctrl_led_mi: DS 1
+ctrl_led_ri: DS 1
+ctrl_led_ro: DS 1
+ctrl_led_io: DS 1
+ctrl_led_ii: DS 1
+ctrl_led_ai: DS 1
+ctrl_led_ao: DS 1
+
+ctrl_led_eo: DS 1
+ctrl_led_su: DS 1
+ctrl_led_bi: DS 1
+ctrl_led_oi: DS 1
+ctrl_led_ce: DS 1
+ctrl_led_co: DS 1
+ctrl_led_jp: DS 1
+ctrl_led_fi: DS 1
+
+flag_led_c: DS 1
+flag_led_z: DS 1
+
+display: DS 3 ; 3 digits
+
+LedEnd:
+
diff --git a/code/ops.asm b/code/ops.asm
new file mode 100644
index 0000000..0844ee5
--- /dev/null
+++ b/code/ops.asm
@@ -0,0 +1,259 @@
+SECTION "Operations", ROM0
+
+; For all instructions, b contains the current op stage
+
+; [in] a: instruction
+; [in] b: stage index
+; 0b0000
+op_hlt:
+  ld c, a
+  ld a, b
+
+  cp 2
+  jr nz, .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_HT, [hl]
+
+.exit:
+  ld c, a
+  ret
+
+; 0b0001
+op_lda:
+  ld c, a
+  ld a, b
+
+  cp 2
+  jr z, .stage_2
+  cp 3
+  jr z, .stage_3
+  jr .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_MI, [hl]
+  set CTRL_IO, [hl]
+  jr .exit
+
+.stage_3:
+  ld hl, ctrl
+  set CTRL_RO, [hl]
+  set CTRL_AI, [hl]
+
+.exit:
+  ld c, a
+  ret
+
+; 0b0010
+op_add:
+  ld c, a
+  ld a, b
+
+  cp 2
+  jr z, .stage_2
+  cp 3
+  jr z, .stage_3
+  cp 4
+  jr z, .stage_4
+  jr .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_MI, [hl]
+  set CTRL_IO, [hl]
+  jr .exit
+
+.stage_3:
+  ld hl, ctrl
+  set CTRL_RO, [hl]
+  inc hl
+  set CTRL_BI, [hl]
+  jr .exit
+
+.stage_4:
+  ld hl, ctrl
+  set CTRL_AI, [hl]
+  inc hl
+  set CTRL_EO, [hl]
+  set CTRL_FI, [hl]
+
+.exit:
+  ld c, a
+  ret
+
+; 0b0011
+op_sub:
+  ld c, a
+  ld a, b
+  cp 2
+  jr z, .stage_2
+  cp 3
+  jr z, .stage_3
+  cp 4
+  jr z, .stage_4
+  jr .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_MI, [hl]
+  set CTRL_IO, [hl]
+  jr .exit
+
+.stage_3:
+  ld hl, ctrl
+  set CTRL_RO, [hl]
+  inc hl
+  set CTRL_BI, [hl]
+  jr .exit
+
+.stage_4:
+  ld hl, ctrl
+  set CTRL_AI, [hl]
+  inc hl
+  set CTRL_EO, [hl]
+  set CTRL_SU, [hl]
+  set CTRL_FI, [hl]
+
+.exit:
+  ld c, a
+  ret
+
+; 0b0100
+op_sta:
+  ld c, a
+  ld a, b
+
+  cp 2
+  jr z, .stage_2
+  cp 3
+  jr z, .stage_3
+  jr .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_MI, [hl]
+  set CTRL_IO, [hl]
+  jr .exit
+
+.stage_3:
+  ld hl, ctrl
+  set CTRL_AO, [hl]
+  set CTRL_RI, [hl]
+
+.exit:
+  ld c, a
+  ret
+
+; 0b0101
+op_ldi:
+  ld c, a
+  ld a, b
+
+  cp 2
+  jr nz, .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_IO, [hl]
+  set CTRL_AI, [hl]
+
+.exit:
+  ld c, a
+  ret
+
+; 0b0110
+op_jmp:
+  ld c, a
+  ld a, b
+
+  cp 2
+  jr nz, .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_IO, [hl]
+  inc hl
+  set CTRL_JP, [hl]
+
+.exit:
+  ld c, a
+  ret
+
+; [in] a: instruction
+; [in] b: stage index
+; 0b0111
+op_jc:
+  ld c, a ; save instruction
+  ld a, b
+
+  cp 2
+  jr nz, .exit
+
+.stage_2:
+  ; save stage index
+  ld d, a
+
+  ld hl, ctrl
+  set CTRL_IO, [hl]
+  inc hl
+
+  ld a, [flags]
+  bit FLAG_C, a
+  jr z, .exit
+  set CTRL_JP, [hl]
+
+.exit:
+  ; restore stage index
+  ld a, d
+  ld c, a
+  ret
+
+; [in] a: instruction
+; [in] b: stage index
+; 0b1000
+op_jz:
+  ld c, a ; save instruction
+  ld a, b
+
+  cp 2
+  jr nz, .exit
+
+.stage_2:
+  ; save stage index
+  ld d, a
+
+  ld hl, ctrl
+  set CTRL_IO, [hl]
+  inc hl
+
+  ld a, [flags]
+  bit FLAG_Z, a
+  jr z, .exit
+  set CTRL_JP, [hl]
+
+.exit:
+  ; restore stage index
+  ld a, d
+  ld c, a
+  ret
+
+; 0b1111
+op_out:
+  ld c, a
+  ld a, b
+
+  cp 2
+  jr nz, .exit
+
+.stage_2:
+  ld hl, ctrl
+  set CTRL_AO, [hl]
+  inc hl
+  set CTRL_OI, [hl]
+
+.exit:
+  ld c, a
+  ret
+
diff --git a/code/signals.asm b/code/signals.asm
new file mode 100644
index 0000000..01c60ef
--- /dev/null
+++ b/code/signals.asm
@@ -0,0 +1,254 @@
+SECTION "Control Signals", ROM0
+
+; [in] f: flags set from a previous operation
+UpdateFlags:
+  ld hl, flags_temp
+
+.check_z:
+  jr z, .set_z
+  res FLAG_Z, [hl]
+
+.check_c:
+  jr c, .set_c
+  res FLAG_C, [hl]
+  jr .exit
+
+.set_z:
+  set FLAG_Z, [hl]
+  jr .check_c
+
+.set_c:
+  set FLAG_C, [hl]
+
+.exit:
+  ret
+
+
+ctrl_ht:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_HT, b
+  jr z, .exit
+
+  xor a
+  ld [running], a
+
+.exit:
+  ret
+
+ctrl_ro:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_RO, b
+  jr z, .exit
+
+  ; get memory offset based on MAR
+  ld hl, ram
+  ld a, [mar]
+  add l
+  ld l, a
+
+  ld a, [hl]
+  ld [bus], a
+
+.exit:
+  ret
+
+ctrl_io:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_IO, b
+  jr z, .exit
+
+  ld a, [ir]
+  and $0f
+  ld [bus], a
+
+.exit:
+  ret
+
+ctrl_ao:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_AO, b
+  jr z, .exit
+
+  ld a, [a_reg]
+  ld [bus], a
+
+.exit:
+  ret
+
+ctrl_eo:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_EO, b
+  jp z, .exit
+
+  ld a, [alu]
+  ld [bus], a
+
+.exit:
+  ret
+
+ctrl_co:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_CO, b
+  jp z, .exit
+
+  ld a, [pc]
+  ld [bus], a
+
+.exit:
+  ret
+
+ctrl_mi:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_MI, b
+  jp z, .exit
+
+  ld a, [bus]
+  ld [mar], a
+
+.exit:
+  ret
+
+ctrl_ri:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_RI, b
+  jp z, .exit
+
+  ; get memory offset based on MAR
+  ld hl, ram
+  ld a, [mar]
+  add l
+  ld l, a
+
+  ld a, [bus]
+  ld [hl], a
+
+.exit:
+  ret
+
+ctrl_ii:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_II, b
+  jp z, .exit
+
+  ld a, [bus]
+  ld [ir], a
+
+.exit:
+  ret
+
+ctrl_ai:
+  ld a, [ctrl]
+  ld b, a
+  bit CTRL_AI, b
+  jp z, .exit
+
+  ld a, [bus]
+  ld [a_reg], a
+  ; alu value reflects any change to A or B
+  ld d, a
+  ld a, [b_reg]
+  add d
+  ld [alu], a
+
+  call UpdateFlags
+
+.exit:
+  ret
+
+ctrl_su:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_SU, b
+  jp z, .exit
+
+  ld a, [b_reg]
+  cpl
+  inc a
+  ld [b_reg], a
+  ; alu value reflects any change to A or B
+  ld d, a
+  ld a, [a_reg]
+  add d
+  ld [alu], a
+
+  call UpdateFlags
+
+.exit:
+  ret
+
+ctrl_bi:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_BI, b
+  jp z, .exit
+
+  ld a, [bus]
+  ld [b_reg], a
+  ; alu value reflects any change to A or B
+  ld d, a
+  ld a, [a_reg]
+  add d
+  ld [alu], a
+
+  call UpdateFlags
+
+.exit:
+  ret
+
+ctrl_oi:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_OI, b
+  jp z, .exit
+
+  ld a, [bus]
+  ld [out_reg], a
+
+.exit:
+  ret
+
+ctrl_ce:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_CE, b
+  jp z, .exit
+
+  ld a, [pc]
+  inc a
+  ld [pc], a
+
+.exit:
+  ret
+
+ctrl_jp:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_JP, b
+  jp z, .exit
+
+  ld a, [bus]
+  ld [pc], a
+
+.exit:
+  ret
+
+ctrl_fi:
+  ld a, [ctrl+1]
+  ld b, a
+  bit CTRL_FI, b
+  jp z, .exit
+
+  ld a, [flags_temp]
+  ld [flags], a
+
+.exit:
+  ret
diff --git a/code/tick.asm b/code/tick.asm
new file mode 100644
index 0000000..1deaf05
--- /dev/null
+++ b/code/tick.asm
@@ -0,0 +1,294 @@
+; [in]  a: value to calculate
+; [out] e: 100s place
+; [out] c: 10s place
+; [out] d: 1s place
+CalculateBCD:
+  ld e, 0 ; count (100s place)
+
+  ld b, 100
+.sub_led_100:
+  ld h, a ; save for 10s calc
+  sub b
+  jr c, .reset
+  ; count++
+  ld c, a
+  ld a, e
+  inc a
+  ld e, a
+  ld a, c
+  jr .sub_led_100
+.reset:
+  ld b, 10
+  ld c, 0 ; count (10s place)
+  ld a, h
+.sub_led_10:
+  sub b
+  jr c, .mod
+  ; count++
+  ld d, a
+  ld a, c
+  inc a
+  ld c, a
+  ld a, d
+  jr .sub_led_10
+.mod:
+  ; a contains overflow; difference is remainder ($ff-remainder-9)
+  ld b, a
+  ld a, $ff
+  sub b
+  ld b, a
+  ld a, 9
+  sub b
+  ; 1s place
+  ld d, a
+  ret
+
+; [in] a:  Value to LED-ify
+; [in] hl: Start address of LED tile
+; [in] c:  LED count
+UpdateLeds:
+  ld b, a  ; cached A
+  dec hl   ; pre-decrement, will be added back first way around the loop
+  ld de, $00FF ; offset from HL (inc e will overflow to 0 for first offset)
+
+  ; shift left for anything less than a count of 8 so we have MSB in the right spot for left shift
+  ld a, 8
+  sub c
+  jr z, .check
+
+.shift:
+  sla b
+  dec a
+  jr nz, .shift
+
+.check:
+  inc hl
+
+  ; determine if we've checked all bits
+  inc e
+  ld a, e
+  cp c
+  jr z, .exit
+
+  ; shift left, carry contains whether the bit was set
+  sla b
+  jr c, .set
+
+.clear:
+  ld [hl], LED_OFF
+  jr .check
+
+.set:
+  ld [hl], LED_ON
+  jr .check
+
+.exit:
+  ret
+
+Tick:
+  ; We don't want any interrupts mid-tick
+  di
+
+  ; Reset the control signals
+  xor a
+  ld hl, ctrl
+  ld [hl+], a
+  ld [hl], a
+
+  ; Reset bus; in case we have no control signals
+  ld [bus], a
+
+  ; Operate based on current op stage
+  ld a, [opc]
+  ld c, a
+
+  ; Stage 0 and 1 are the same for all operations
+  cp $0
+  jr z, .stage_0
+  cp $1
+  jr z, .stage_1
+
+  ; Stage 2, 3, and 4 differ
+  jr .stage_2_3_4
+
+  ; Stage 0 same for all instructions: CO | MI
+.stage_0:
+  ld hl, ctrl
+  set CTRL_MI, [hl]
+  inc hl
+  set CTRL_CO, [hl]
+  jr .update_leds
+
+  ; Stage 1 same for all instructions: RO | II | CE
+.stage_1:
+  ld hl, ctrl
+  set CTRL_RO, [hl]
+  set CTRL_II, [hl]
+  inc hl
+  set CTRL_CE, [hl]
+  jr .update_leds
+
+.stage_2_3_4:
+  ld a, [ir]
+  and $f0
+  ld b, c
+
+  ; NOP
+  cp $00
+  jr z, .update_leds
+
+  ; LDA
+  cp $10
+  call z, op_lda
+
+  ; ADD
+  cp $20
+  call z, op_add
+
+  ; SUB
+  cp $30
+  call z, op_sub
+
+  ; STA
+  cp $40
+  call z, op_sta
+
+  ; LDI
+  cp $50
+  call z, op_ldi
+
+  ; JP
+  cp $60
+  call z, op_jmp
+
+  ; JC
+  cp $70
+  call z, op_jc
+
+  ; JZ
+  cp $80
+  call z, op_jz
+
+  ; OUT
+  cp $e0
+  call z, op_out
+
+  ; HLT
+  cp $f0
+  call z, op_hlt
+
+.update_leds:
+  ; These LEDs are latched by the clock so we want to display only pre-control signal evaluation
+  ld a, [opc]
+  ld c, 3
+  ld hl, opc_led_2
+  call UpdateLeds
+
+  ld a, [pc]
+  ld c, 4
+  ld hl, pc_led_3
+  call UpdateLeds
+
+  ld a, [mar]
+  ld c, 4
+  ld hl, mar_led_3
+  call UpdateLeds
+
+  ld a, [ir]
+  ld c, 8
+  ld hl, ir_led_7
+  call UpdateLeds
+
+  ld a, [a_reg]
+  ld c, 8
+  ld hl, a_led_7
+  call UpdateLeds
+
+  ld a, [b_reg]
+  ld c, 8
+  ld hl, b_led_7
+  call UpdateLeds
+
+  ld a, [alu]
+  ld c, 8
+  ld hl, alu_led_7
+  call UpdateLeds
+
+  ld a, [ctrl]
+  ld c, 8
+  ld hl, ctrl_led_ht
+  call UpdateLeds
+
+  ld a, [ctrl+1]
+  ld c, 8
+  ld hl, ctrl_led_eo
+  call UpdateLeds
+
+  ld a, [flags]
+  ld c, 2
+  ld hl, flag_led_c
+  call UpdateLeds
+
+  ; Update output display
+  ld a, [out_reg]
+  call CalculateBCD
+  ; 100s place
+  ld hl, display
+  ld [hl], e
+  ; 10s place
+  inc hl
+  ld [hl], c
+  ; 1s place
+  inc hl
+  ld [hl], d
+
+  ; Update mem display
+  ld a, [mar]
+  ld hl, ram
+  add l
+  ld l, a
+  ld a, [hl]
+  ld [mem], a
+
+  ; Update the control signals for next time. Order matters.
+  call ctrl_ht
+  call ctrl_ro
+  call ctrl_io
+  call ctrl_ao
+  call ctrl_su
+  call ctrl_fi
+  call ctrl_eo
+  call ctrl_co
+  call ctrl_mi
+  call ctrl_ri
+  call ctrl_ii
+  call ctrl_ai
+  call ctrl_bi
+  call ctrl_oi
+  call ctrl_ce
+  call ctrl_jp
+
+  ; The memory LEDs are also instantaneous (they display whatever is in memory at the address in the MAR)
+  ld a, [mem]
+  ld c, 8
+  ld hl, mem_led_7
+  call UpdateLeds
+
+  ; The bus LEDs are instantaneous (no latching), so we should always display latest
+  ld a, [bus]
+  ld c, 8
+  ld hl, bus_led_7
+  call UpdateLeds
+
+  ; Go to next op stage
+  ld a, [opc]
+  inc a
+  ld [opc], a
+  cp 5
+  jr nz, .exit
+  xor a
+  ld [opc], a
+
+.exit:
+  ei
+  ret