2023-fpga-computer/src/sap2/ir.v

module ir(
	input clk,
	input clr,
	input load,
	input[15:0] bus,
	output[7:0] out
);

reg[7:0] data = 0;

always @(posedge clk or posedge clr) begin
	if (clr) begin
		data <= 8'b0;
	end else if (load) begin
		data <= bus[7:0];
	end
end

assign out = data;

endmodule