2023-fpga-computer/src/sap2/pc.v

module pc(
	input clk,
	input clr,
	input inc,
	input load,
	input en,
	output[15:0] bus
);

reg[15:0] pc = 0;

always @(posedge clk or posedge clr) begin
	if (clr) begin
		pc <= 16'b0;
	end else if (load) begin
		pc <= bus;
	end else if (inc) begin
		pc <= pc + 1;
	end
end

assign bus = (en) ? pc : 16'bz;

endmodule