2023-fpga-computer/src/sap2/top.v

module top(
	input CLK
);


wire[15:0] bus;
wire clr;
wire hlt;


wire clk;
clock clock(
	// In
	.hlt(hlt),
	.clk_in(CLK),

	// Out
	.clk_out(clk)
);

wire pc_inc;
wire pc_load;
wire pc_en;
pc pc(
	// In
	.clk(clk),
	.clr(clr),
	.inc(pc_inc),
	.load(pc_load),
	.en(pc_en),

	// Output
	.bus(bus)
);

wire ir_load;
wire[7:0] ir_instr;
ir ir(
	// In
	.clk(clk),
	.clr(clr),
	.load(ir_load),

	// Inout
	.bus(bus),

	// Out
	.out(ir_instr)
);

wire mar_loadh;
wire mar_loadl;
wire mdr_load;
wire mdr_en;
wire ram_load;
wire ram_enh;
wire ram_enl;
wire call;
wire ret;
memory mem(
	// In
	.clk(clk),
	.mar_loadh(mar_loadh),
	.mar_loadl(mar_loadl),
	.mdr_load(mdr_load),
	.mdr_en(mdr_en),
	.ram_load(ram_load),
	.ram_enh(ram_enh),
	.ram_enl(ram_enl),
	.call(call),
	.ret(ret),

	// Inout
	.bus(bus)
);

wire a_load;
wire a_en;
wire a_inc;
wire a_dec;
wire[7:0] a_val;
register reg_a(
	// In
	.clk(clk),
	.load(a_load),
	.en(a_en),
	.inc(a_inc),
	.dec(a_dec),

	// Inout
	.bus(bus),

	// Out
	.out(a_val)
);

wire b_load;
wire b_en;
wire b_inc;
wire b_dec;
wire[7:0] b_val;
register reg_b(
	// In
	.clk(clk),
	.load(b_load),
	.en(b_en),
	.inc(b_inc),
	.dec(b_dec),

	// Inout
	.bus(bus),

	// Out
	.out(b_val)
);

wire c_load;
wire c_en;
wire c_inc;
wire c_dec;
wire[7:0] c_val;
register reg_c(
	// In
	.clk(clk),
	.load(c_load),
	.en(c_en),
	.inc(c_inc),
	.dec(c_dec),

	// Inout
	.bus(bus),

	// Out
	.out(c_val)
);

wire[2:0] alu_op;
wire alu_load;
wire alu_en;
alu alu(
	// In
	.clk(clk),
	.a(a_val),
	.load(alu_load),
	.op(alu_op),
	.en(alu_en),

	// Out
	.bus(bus)
);

wire[1:0] flags_val;
wire flags_lda;
wire flags_ldb;
wire flags_ldc;
flags flags(
	// In
	.clk(clk),
	.a(a_val),
	.b(b_val),
	.c(c_val),
	.load_a(flags_lda),
	.load_b(flags_ldb),
	.load_c(flags_ldc),

	// Out
	.out(flags_val)
);

controller controller(
	.clk(clk),
	.instr(ir_instr),
	.flags(flags_val),
	.ctrl_word({
		hlt,
		a_load,
		a_en,
		a_inc,
		a_dec,
		b_load,
		b_en,
		b_inc,
		b_dec,
		c_load,
		c_en,
		c_inc,
		c_dec,
		flags_lda,
		flags_ldb,
		flags_ldc,
		alu_op,
		alu_load,
		alu_en,
		ir_load,
		pc_inc,
		pc_load,
		pc_en,
		mar_loadh,
		mar_loadl,
		mdr_load,
		mdr_en,
		ram_load,
		ram_enh,
		ram_enl,
		call,
		ret})
);

endmodule