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2023-fpga-computer/src/sap1/pc.v

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2023-01-04 02:26:45 +00:00
module pc(
input clk,
input clr,
input inc,
input en,
output[7:0] bus
);
reg[3:0] pc = 0;
always @(posedge clk or posedge clr) begin
if (clr) begin
pc <= 4'b0;
end else if (inc) begin
pc <= pc + 1;
end
end
assign bus = (en) ? pc : 8'bz;
endmodule