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2023-fpga-computer/src/sap2/register.v

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module register(
input clk,
input rst,
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input load,
input inc,
input dec,
input[15:0] bus,
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output[7:0] out
);
reg[7:0] data;
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always @(posedge clk, posedge rst) begin
if (rst) begin
data <= 8'b0;
end else if (load) begin
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data <= bus[7:0];
end else if (inc) begin
data <= data + 1;
end else if (dec) begin
data <= data - 1;
end
end
assign out = data;
endmodule