Add rst and remove en from SAP-1 and SAP-2
parent
03d0d5c982
commit
eb7cc9dc79
@ -1,23 +1,22 @@
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module ir(
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input clk,
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input clr,
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input rst,
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input load,
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input en,
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inout[7:0] bus,
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output[3:0] instr);
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input[7:0] bus,
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output[7:0] out
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);
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reg[7:0] ir = 0;
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reg[7:0] ir;
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always @(posedge clk or posedge clr) begin
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if (clr) begin
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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ir <= 8'b0;
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end else if (load) begin
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ir <= bus;
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end
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end
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assign instr = ir[7:4];
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assign bus = (en) ? ir[3:0] : 8'bz;
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assign out = ir;
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endmodule
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@ -1,24 +1,27 @@
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module memory(
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input clk,
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input rst,
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input load,
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input en,
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inout[7:0] bus
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input[7:0] bus,
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output[7:0] out
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);
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initial begin
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$readmemh("program.bin", ram);
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end
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reg[3:0] mar = 0;
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reg[3:0] mar;
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reg[7:0] ram[0:15];
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always @(posedge clk) begin
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if (load) begin
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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mar <= 4'b0;
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end else if (load) begin
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mar <= bus[3:0];
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end
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end
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assign bus = (en) ? ram[mar] : 8'bz;
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assign out = ram[mar];
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endmodule
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@ -1,22 +1,21 @@
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module pc(
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input clk,
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input clr,
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input rst,
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input inc,
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input en,
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output[7:0] bus
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output[7:0] out
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);
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reg[3:0] pc = 0;
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reg[3:0] pc;
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always @(posedge clk or posedge clr) begin
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if (clr) begin
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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pc <= 4'b0;
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end else if (inc) begin
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pc <= pc + 1;
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end
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end
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assign bus = (en) ? pc : 8'bz;
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assign out = pc;
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endmodule
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@ -1,20 +1,22 @@
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module reg_a(
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input clk,
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input rst,
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input load,
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input en,
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inout[7:0] bus,
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output[7:0] val);
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input[7:0] bus,
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output[7:0] out
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);
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reg[7:0] reg_a = 0;
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reg[7:0] reg_a;
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always @(posedge clk) begin
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if (load) begin
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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reg_a <= 8'b0;
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end else if (load) begin
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reg_a <= bus;
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end
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end
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assign bus = (en) ? reg_a : 8'bz;
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assign val = reg_a;
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assign out = reg_a;
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endmodule
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@ -1,18 +1,22 @@
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module reg_b(
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input clk,
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input rst,
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input load,
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input[7:0] bus,
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output[7:0] val);
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output[7:0] out
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);
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reg[7:0] reg_b = 0;
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reg[7:0] reg_b;
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always @(posedge clk) begin
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if (load) begin
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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reg_b <= 8'b0;
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end else if (load) begin
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reg_b <= bus;
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end
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end
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assign val = reg_b;
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assign out = reg_b;
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endmodule
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@ -1,22 +1,22 @@
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module ir(
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input clk,
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input clr,
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input rst,
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input load,
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input[15:0] bus,
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output[7:0] out
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);
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reg[7:0] data = 0;
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reg[7:0] ir;
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always @(posedge clk or posedge clr) begin
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if (clr) begin
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data <= 8'b0;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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ir <= 8'b0;
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end else if (load) begin
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data <= bus[7:0];
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ir <= bus[7:0];
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end
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end
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assign out = data;
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assign out = ir;
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endmodule
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