module top_tb();

initial begin
	$dumpfile("top_tb.vcd");
	$dumpvars(0, top_tb);
end

reg clk_in = 0;
integer i;
initial begin
	for (i = 0; i < 128; i++) begin
		#1 clk_in = ~clk_in;
	end
end

wire clk;
wire hlt;
wire clr;
wire[7:0] bus;

clock clock(
	.hlt(hlt),
	.clk_in(clk_in),
	.clk_out(clk)
);

wire pc_en;
wire pc_inc;
pc pc(
	.clk(clk),
	.clr(clr),
	.inc(pc_inc),
	.en(pc_en),
	.bus(bus)
);

wire a_load;
wire a_en;
wire[7:0] a_val;
reg_a reg_a(
	.clk(clk),
	.load(a_load),
	.en(a_en),
	.bus(bus),
	.val(a_val)
);

wire b_load;
wire[7:0] b_val;
reg_b reg_b(
	.clk(clk),
	.load(b_load),
	.bus(bus),
	.val(b_val)
);

wire adder_sub;
wire adder_en;
adder adder(
	.a(a_val),
	.b(b_val),
	.sub(adder_sub),
	.en(adder_en),
	.bus(bus)
);

wire mar_load;
wire mem_en;
memory mem(
	.clk(clk),
	.load(mar_load),
	.en(mem_en),
	.bus(bus)
);

wire ir_load;
wire ir_en;
wire[3:0] ir_instr;
ir ir(
	.clk(clk),
	.clr(clr),
	.load(ir_load),
	.en(ir_en),
	.bus(bus),
	.instr(ir_instr)
);

controller controller(
	.clk(clk),
	.instr(ir_instr),
	.ctrl_word(
	{
		hlt,
		pc_inc,
		pc_en,
		mar_load,
		mem_en,
		ir_load,
		ir_en,
		a_load,
		a_en,
		b_load,
		adder_sub,
		adder_en
	})
);

endmodule