module memory(
	input clk,
	input load,
	input en,
	inout[7:0] bus
);

initial begin
	$readmemh("program.bin", ram);
end

reg[3:0] mar = 0;
reg[7:0] ram[0:15];

always @(posedge clk) begin
	if (load) begin
		mar <= bus[3:0];
	end
end

assign bus = (en) ? ram[mar] : 8'bz;

endmodule