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23 lines
249 B

module ir(
input clk,
input rst,
input load,
input[7:0] bus,
output[7:0] out
reg[7:0] ir;
always @(posedge clk, posedge rst) begin
if (rst) begin
ir <= 8'b0;
end else if (load) begin
ir <= bus;
assign out = ir;