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28 lines
338 B
Verilog
28 lines
338 B
Verilog
module memory(
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input clk,
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input rst,
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input load,
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input[7:0] bus,
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output[7:0] out
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);
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initial begin
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$readmemh("program.bin", ram);
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end
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reg[3:0] mar;
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reg[7:0] ram[0:15];
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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mar <= 4'b0;
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end else if (load) begin
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mar <= bus[3:0];
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end
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end
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assign out = ram[mar];
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endmodule
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