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module reg_b(
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input clk,
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input rst,
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input load,
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input[7:0] bus,
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output[7:0] out
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);
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reg[7:0] reg_b;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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reg_b <= 8'b0;
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end else if (load) begin
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reg_b <= bus;
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end
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end
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assign out = reg_b;
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endmodule
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