137 lines
1.5 KiB
Verilog
137 lines
1.5 KiB
Verilog
module top_tb();
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initial begin
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$dumpfile("top_tb.vcd");
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$dumpvars(0, top_tb);
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rst = 1;
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#1 rst = 0;
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end
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reg[7:0] bus;
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always @(*) begin
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if (ir_en) begin
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bus = ir_out;
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end else if (adder_en) begin
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bus = adder_out;
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end else if (a_en) begin
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bus = a_out;
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end else if (mem_en) begin
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bus = mem_out;
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end else if (pc_en) begin
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bus = pc_out;
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end else begin
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bus = 8'b0;
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end
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end
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reg clk_in = 0;
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integer i;
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initial begin
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for (i = 0; i < 128; i++) begin
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#1 clk_in = ~clk_in;
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end
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end
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wire clk;
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wire hlt;
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reg rst;
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clock clock(
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.hlt(hlt),
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.clk_in(clk_in),
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.clk_out(clk)
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);
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wire pc_inc;
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wire[7:0] pc_out;
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wire pc_en;
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pc pc(
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.clk(clk),
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.rst(rst),
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.inc(pc_inc),
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.out(pc_out)
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);
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wire mar_load;
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wire mem_en;
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wire[7:0] mem_out;
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memory mem(
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.clk(clk),
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.rst(rst),
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.load(mar_load),
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.bus(bus),
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.out(mem_out)
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);
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wire a_load;
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wire a_en;
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wire[7:0] a_out;
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reg_a reg_a(
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.clk(clk),
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.rst(rst),
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.load(a_load),
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.bus(bus),
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.out(a_out)
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);
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wire b_load;
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wire[7:0] b_out;
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reg_b reg_b(
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.clk(clk),
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.rst(rst),
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.load(b_load),
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.bus(bus),
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.out(b_out)
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);
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wire adder_sub;
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wire adder_en;
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wire[7:0] adder_out;
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adder adder(
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.a(a_out),
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.b(b_out),
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.sub(adder_sub),
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.out(adder_out)
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);
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wire ir_load;
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wire ir_en;
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wire[7:0] ir_out;
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ir ir(
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.clk(clk),
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.rst(rst),
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.load(ir_load),
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.bus(bus),
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.out(ir_out)
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);
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controller controller(
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.clk(clk),
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.rst(rst),
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.opcode(ir_out[7:4]),
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.out(
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{
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hlt,
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pc_inc,
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pc_en,
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mar_load,
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mem_en,
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ir_load,
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ir_en,
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a_load,
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a_en,
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b_load,
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adder_sub,
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adder_en
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})
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);
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endmodule
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