68 lines
898 B
Verilog
68 lines
898 B
Verilog
module alu(
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input clk,
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input rst,
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input[7:0] a,
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input[2:0] op,
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input load,
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input[15:0] bus,
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output[7:0] out
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);
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reg[7:0] alu;
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reg[7:0] tmp;
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localparam OP_ADD = 0;
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localparam OP_SUB = 1;
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localparam OP_AND = 2;
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localparam OP_OR = 3;
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localparam OP_XOR = 4;
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localparam OP_CMA = 5;
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localparam OP_RAL = 6;
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localparam OP_RAR = 7;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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tmp <= 8'b0;
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end else if (load) begin
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tmp <= bus[7:0];
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end
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end
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always @(*) begin
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case (op)
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OP_ADD: begin
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alu = a + tmp;
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end
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OP_SUB: begin
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alu = a - tmp;
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end
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OP_AND: begin
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alu = a & tmp;
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end
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OP_OR: begin
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alu = a | tmp;
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end
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OP_XOR: begin
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alu = a ^ tmp;
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end
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OP_CMA: begin
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alu = ~a;
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end
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OP_RAL: begin
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alu = a << 1;
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alu[0] = a[7];
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end
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OP_RAR: begin
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alu = a >> 1;
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end
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default: begin
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alu = 0;
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end
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endcase
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end
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assign out = alu;
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endmodule
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