90 lines
2.0 KiB
Verilog
90 lines
2.0 KiB
Verilog
module controller(
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input clk,
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input rst,
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input[7:0] opcode,
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input[1:0] flags,
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output[33:0] out
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);
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localparam SIG_END = 34;
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localparam SIG_HLT = 33;
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localparam SIG_A_LOAD = 32;
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localparam SIG_A_EN = 31;
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localparam SIG_A_INC = 30;
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localparam SIG_A_DEC = 29;
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localparam SIG_B_LOAD = 28;
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localparam SIG_B_EN = 27;
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localparam SIG_B_INC = 26;
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localparam SIG_B_DEC = 25;
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localparam SIG_C_LOAD = 24;
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localparam SIG_C_EN = 23;
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localparam SIG_C_INC = 22;
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localparam SIG_C_DEC = 21;
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localparam SIG_FLAGS_LDA = 20;
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localparam SIG_FLAGS_LDB = 19;
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localparam SIG_FLAGS_LDC = 18;
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localparam SIG_ALU_OP2 = 17;
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localparam SIG_ALU_OP1 = 16;
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localparam SIG_ALU_OP0 = 15;
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localparam SIG_ALU_LD = 14;
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localparam SIG_ALU_EN = 13;
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localparam SIG_IR_LOAD = 12;
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localparam SIG_PC_INC = 11;
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localparam SIG_PC_LOAD = 10;
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localparam SIG_PC_EN = 9;
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localparam SIG_MAR_LOADH = 8;
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localparam SIG_MAR_LOADL = 7;
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localparam SIG_MDR_LOAD = 6;
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localparam SIG_MDR_EN = 5;
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localparam SIG_RAM_LOAD = 4;
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localparam SIG_RAM_ENH = 3;
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localparam SIG_RAM_ENL = 2;
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localparam SIG_CALL = 1;
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localparam SIG_RET = 0;
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localparam OP_JZ = 8'hCA;
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localparam OP_JNZ = 8'hC2;
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localparam OP_JM = 8'hFA;
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localparam FLAG_Z = 1;
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localparam FLAG_S = 0;
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reg[34:0] ctrl_word;
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reg[34:0] ctrl_rom[0:4095];
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initial begin
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$readmemb("ctrl_rom.bin", ctrl_rom);
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end
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reg[3:0] stage;
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always @(negedge clk, posedge rst) begin
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if (rst) begin
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stage <= 0;
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end else begin
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if (stage_rst) begin
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stage <= 0;
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end else begin
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stage <= stage + 1;
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end
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end
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end
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reg stage_rst;
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always @(*) begin
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ctrl_word = ctrl_rom[{opcode, stage}];
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if ((opcode == OP_JZ && stage == 4 && flags[FLAG_Z] == 0) ||
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(opcode == OP_JNZ && stage == 4 && flags[FLAG_Z] == 1) ||
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(opcode == OP_JM && stage == 4 && flags[FLAG_S] == 0))
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begin
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stage_rst = 1;
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end else begin
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stage_rst = ctrl_rom[{opcode, stage}][SIG_END];
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end
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end
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assign out = ctrl_word;
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endmodule
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