61 lines
916 B
Verilog
61 lines
916 B
Verilog
module memory(
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input clk,
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input rst,
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input mar_loadh,
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input mar_loadl,
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input mdr_load,
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input ram_load,
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input ram_enh,
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input ram_enl,
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input call,
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input ret,
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input[15:0] bus,
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output[15:0] out
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);
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initial begin
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$readmemh("program.bin", ram);
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end
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reg[15:0] mar;
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reg[15:0] mdr;
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reg[7:0] ram[0:65535];
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always @(posedge rst) begin
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mar <= 16'b0;
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mdr <= 16'b0;
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end
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always @(posedge clk) begin
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if (mar_loadh) begin
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mar[15:8] <= bus[15:8];
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end
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if (mar_loadl) begin
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mar[7:0] <= bus[7:0];
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end
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if (mdr_load) begin
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mdr[7:0] <= bus[7:0];
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end
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if (ret) begin
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mdr[15:8] <= ram[16'hFFFE];
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mdr[7:0] <= ram[16'hFFFF];
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end else if (call) begin
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ram[16'hFFFE] <= bus[15:8];
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ram[16'hFFFF] <= bus[7:0];
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end else if (ram_enh) begin
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mdr[15:8] <= ram[mar];
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end else if (ram_enl) begin
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mdr[7:0] <= ram[mar];
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end else if (ram_load) begin
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ram[mar] <= mdr;
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end
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end
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assign out = mdr;
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endmodule
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