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193 lines
2.5 KiB

module top_tb();
initial begin
$dumpvars(0, top_tb);
rst = 1;
#1 rst = 0;
reg[15:0] bus;
always @(*) begin
if (a_en) begin
bus = a_out;
end else if (b_en) begin
bus = b_out;
end else if (c_en) begin
bus = c_out;
end else if (alu_en) begin
bus = alu_out;
end else if (pc_en) begin
bus = pc_out;
end else if (mdr_en) begin
bus = mem_out;
end else begin
bus = 16'b0;
reg clk_in = 0;
integer i;
initial begin
for (i = 0; i < 512; i++) begin
#1 clk_in = ~clk_in;
reg rst;
wire hlt;
wire clk;
clock clock(
wire pc_inc;
wire pc_load;
wire pc_en;
wire[15:0] pc_out;
pc pc(
wire ir_load;
wire[7:0] ir_out;
ir ir(
wire mar_loadh;
wire mar_loadl;
wire mdr_load;
wire mdr_en;
wire ram_load;
wire ram_enh;
wire ram_enl;
wire call;
wire ret;
wire[15:0] mem_out;
memory mem(
wire a_load;
wire a_en;
wire a_inc;
wire a_dec;
wire[7:0] a_out;
register reg_a(
wire b_load;
wire b_en;
wire b_inc;
wire b_dec;
wire[7:0] b_out;
register reg_b(
wire c_load;
wire c_en;
wire c_inc;
wire c_dec;
wire[7:0] c_out;
register reg_c(
wire[2:0] alu_op;
wire alu_load;
wire alu_en;
wire[7:0] alu_out;
alu alu(
wire[1:0] flags_out;
wire flags_lda;
wire flags_ldb;
wire flags_ldc;
flags flags(
controller controller(
a_load, a_en, a_inc, a_dec,
b_load, b_en, b_inc, b_dec,
c_load, c_en, c_inc, c_dec,
flags_lda, flags_ldb, flags_ldc,
alu_op, alu_load, alu_en,
pc_inc, pc_load, pc_en,
mar_loadh, mar_loadl, mdr_load,
ram_load, ram_enh, ram_enl,
call, ret})