33 lines
406 B
Verilog
33 lines
406 B
Verilog
module memory(
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input clk,
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input rst,
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input mar_we,
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input ram_we,
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input[15:0] bus,
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output[7:0] out
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);
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initial begin
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$readmemh("program.bin", ram);
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end
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reg[15:0] mar;
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reg[7:0] ram[0:255];
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always @(posedge clk, posedge rst) begin
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if (rst)
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mar <= 16'b0;
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else if (mar_we)
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mar <= bus;
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end
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always @(posedge clk) begin
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if (ram_we)
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ram[mar] <= bus[7:0];
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end
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assign out = ram[mar];
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endmodule
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