73 lines
1.7 KiB
Verilog
73 lines
1.7 KiB
Verilog
module reg_file(
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input clk,
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input rst,
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input[4:0] rd_sel,
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input[4:0] wr_sel,
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input[1:0] ext,
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input we,
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input[15:0] data_in,
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output[15:0] data_out
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);
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// 8-bit
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// 0 1
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// 0000_ [ B ][ C ]
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// 0001_ [ D ][ E ]
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// 0010_ [ H ][ L ]
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// 0011_ [ W ][ Z ]
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// 0100_ [ P ][ C ]
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// 0101_ [ S ][ P ]
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// 16-bit (ext)
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//
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// 10000 [ BC ]
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// 10010 [ DE ]
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// 10100 [ HL ]
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// 10110 [ WZ ]
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// 11000 [ PC ]
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// 11010 [ SP ]
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reg[7:0] data[0:11];
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reg[15:0] data_out;
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wire wr_ext = wr_sel[4];
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wire rd_ext = rd_sel[4];
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wire[3:0] wr_dst = wr_sel[3:0];
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wire[3:0] rd_src = rd_sel[3:0];
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localparam EXT_INC = 2'b01;
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localparam EXT_DEC = 2'b10;
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localparam EXT_INC2 = 2'b11;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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data[0] <= 8'b0; data[1] <= 8'b0; data[2] <= 8'b0; data[3] <= 8'b0; data[4] <= 8'b0;
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data[5] <= 8'b0; data[6] <= 8'b0; data[7] <= 8'b0; data[8] <= 8'b0; data[9] <= 8'b0;
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data[10] <= 8'b0; data[11] <= 8'b0;
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end else begin
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if (ext == EXT_INC) begin
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{data[wr_dst], data[wr_dst+1]} <= {data[wr_dst], data[wr_dst+1]} + 1;
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end else if (ext == EXT_INC2) begin
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{data[wr_dst], data[wr_dst+1]} <= {data[wr_dst], data[wr_dst+1]} + 2;
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end else if (ext == EXT_DEC) begin
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{data[wr_dst], data[wr_dst+1]} <= {data[wr_dst], data[wr_dst+1]} - 1;
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end else if (we) begin
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if (wr_ext) begin
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{data[wr_dst], data[wr_dst+1]} <= data_in;
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end else begin
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data[wr_dst] <= data_in[7:0];
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end
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end
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end
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end
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always @(*) begin
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if (rd_ext) begin
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data_out = {data[rd_src], data[rd_src+1]};
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end else begin
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data_out = {8'b0, data[rd_src]};
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end
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end
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endmodule
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