155 lines
2.1 KiB
Verilog
155 lines
2.1 KiB
Verilog
module top_tb();
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initial begin
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$dumpfile("top_tb.vcd");
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$dumpvars(0, top_tb);
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for (i = 0; i < 12; i++) begin
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$dumpvars(0, reg_file.data[i]);
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end
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for (i = 230; i < 256; i++) begin
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$dumpvars(0, memory.ram[i]);
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end
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rst = 1;
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#1 rst = 0;
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end
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reg clk_in = 0;
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integer i;
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initial begin
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for (i = 0; i < 8096; i++) begin
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#1 clk_in = ~clk_in;
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end
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end
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reg[7:0] out;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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out = 8'b0;
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end else if (display) begin
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out = alu_out;
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end
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end
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reg[15:0] bus;
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always @(*) begin
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bus = 16'b0;
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if (reg_oe)
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bus = reg_out;
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else if (mem_oe)
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bus = {8'b0, mem_out};
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else if (alu_oe)
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bus = {8'b0, alu_out};
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else if (alu_flags_oe)
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bus = {8'b0, alu_flags};
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end
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reg rst;
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wire hlt;
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wire clk;
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clock clock(
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.hlt(hlt),
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.clk_in(clk_in),
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.clk_out(clk)
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);
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wire[4:0] reg_rd_sel;
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wire[4:0] reg_wr_sel;
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wire[1:0] reg_ext;
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wire reg_oe;
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wire reg_we;
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wire[15:0] reg_out;
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reg_file reg_file(
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.clk(clk),
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.rst(rst),
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.rd_sel(reg_rd_sel),
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.wr_sel(reg_wr_sel),
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.ext(reg_ext),
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.we(reg_we),
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.data_in(bus),
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.data_out(reg_out)
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);
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wire mem_mar_we;
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wire mem_ram_we;
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wire mem_oe;
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wire[7:0] mem_out;
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memory memory(
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.clk(clk),
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.rst(rst),
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.mar_we(mem_mar_we),
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.ram_we(mem_ram_we),
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.bus(bus),
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.out(mem_out)
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);
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wire ir_we;
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wire[7:0] ir_out;
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ir ir(
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.clk(clk),
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.rst(rst),
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.we(ir_we),
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.bus(bus[7:0]),
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.out(ir_out)
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);
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wire alu_cs;
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wire alu_flags_we;
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wire alu_a_we;
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wire alu_a_store;
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wire alu_a_restore;
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wire alu_tmp_we;
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wire alu_oe;
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wire alu_flags_oe;
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wire[4:0] alu_op;
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wire[7:0] alu_flags;
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wire[7:0] alu_out;
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alu alu(
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.clk(clk),
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.rst(rst),
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.cs(alu_cs),
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.flags_we(alu_flags_we),
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.a_we(alu_a_we),
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.a_store(alu_a_store),
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.a_restore(alu_a_restore),
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.tmp_we(alu_tmp_we),
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.op(alu_op),
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.bus(bus[7:0]),
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.flags(alu_flags),
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.out(alu_out)
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);
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controller controller(
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.clk(clk),
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.rst(rst),
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.opcode(ir_out),
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.flags(alu_flags),
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.out({
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display,
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hlt,
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alu_cs,
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alu_flags_we,
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alu_a_we,
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alu_a_store,
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alu_a_restore,
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alu_tmp_we,
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alu_op,
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alu_oe,
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alu_flags_oe,
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reg_rd_sel,
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reg_wr_sel,
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reg_ext,
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reg_oe,
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reg_we,
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mem_ram_we,
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mem_mar_we,
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mem_oe,
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ir_we
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})
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);
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endmodule
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