98 lines
1019 B
Verilog
98 lines
1019 B
Verilog
module top(
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input CLK);
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wire[7:0] bus;
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wire clk;
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wire hlt;
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clock clock(
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.hlt(hlt),
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.clk_in(CLK),
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.clk_out(clk)
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);
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wire clr;
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wire pc_en;
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wire pc_inc;
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pc pc(
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.clk(clk),
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.clr(clr),
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.inc(pc_inc),
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.en(pc_en),
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.bus(bus)
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);
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wire a_load;
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wire a_en;
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wire[7:0] a_val;
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reg_a reg_a(
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.clk(clk),
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.load(a_load),
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.en(a_en),
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.bus(bus),
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.val(a_val)
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);
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wire b_load;
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wire[7:0] b_val;
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reg_b reg_b(
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.clk(clk),
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.load(b_load),
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.bus(bus),
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.val(b_val)
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);
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wire adder_sub;
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wire adder_en;
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adder adder(
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.a(a_val),
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.b(b_val),
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.sub(adder_sub),
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.en(adder_en),
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.bus(bus)
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);
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wire mar_load;
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wire mem_en;
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memory mem(
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.clk(clk),
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.load(mar_load),
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.en(mem_en),
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.bus(bus)
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);
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wire ir_load;
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wire ir_en;
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wire[3:0] ir_instr;
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ir ir(
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.clk(clk),
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.clr(clr),
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.load(ir_load),
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.en(ir_en),
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.bus(bus),
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.instr(ir_instr)
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);
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controller controller(
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.clk(clk),
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.instr(ir_instr),
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.ctrl_word(
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{
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hlt,
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pc_inc,
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pc_en,
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mar_load,
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mem_en,
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ir_load,
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ir_en,
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a_load,
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a_en,
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b_load,
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adder_sub,
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adder_en
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})
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);
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endmodule
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