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module memory(
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input clk,
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input load,
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input en,
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inout[7:0] bus
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);
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initial begin
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$readmemh("program.bin", ram);
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end
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reg[3:0] mar = 0;
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reg[7:0] ram[0:15];
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always @(posedge clk) begin
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if (load) begin
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mar <= bus[3:0];
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end
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end
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assign bus = (en) ? ram[mar] : 8'bz;
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endmodule
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