1
0
Fork 0
2023-fpga-computer/src/reg_a.v

21 lines
245 B
Verilog

module reg_a(
input clk,
input load,
input en,
inout[7:0] bus,
output[7:0] val);
reg[7:0] reg_a = 0;
always @(posedge clk) begin
if (load) begin
reg_a <= bus;
end
end
assign bus = (en) ? reg_a : 8'bz;
assign val = reg_a;
endmodule