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2023-fpga-computer/src/sap1/ir.v

24 lines
310 B
Verilog

module ir(
input clk,
input clr,
input load,
input en,
inout[7:0] bus,
output[3:0] instr);
reg[7:0] ir = 0;
always @(posedge clk or posedge clr) begin
if (clr) begin
ir <= 8'b0;
end else if (load) begin
ir <= bus;
end
end
assign instr = ir[7:4];
assign bus = (en) ? ir[3:0] : 8'bz;
endmodule