26 lines
320 B
Verilog
26 lines
320 B
Verilog
module pc(
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input clk,
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input clr,
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input inc,
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input load,
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input en,
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output[15:0] bus
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);
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reg[15:0] pc = 0;
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always @(posedge clk or posedge clr) begin
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if (clr) begin
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pc <= 16'b0;
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end else if (load) begin
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pc <= bus;
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end else if (inc) begin
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pc <= pc + 1;
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end
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end
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assign bus = (en) ? pc : 16'bz;
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endmodule
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