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2023-fpga-computer/src/sap2/register.v

28 lines
374 B
Verilog

module register(
input clk,
input load,
input en,
input inc,
input dec,
inout[15:0] bus,
output[7:0] out
);
reg[7:0] data = 0;
always @(posedge clk) begin
if (load) begin
data <= bus[7:0];
end else if (inc) begin
data <= data + 1;
end else if (dec) begin
data <= data - 1;
end
end
assign bus = (en) ? {8'b0, data} : 16'bz;
assign out = data;
endmodule