37 lines
680 B
Verilog
37 lines
680 B
Verilog
module flags(
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input clk,
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input rst,
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input[7:0] a,
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input[7:0] b,
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input[7:0] c,
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input load_a,
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input load_b,
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input load_c,
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output[1:0] out
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);
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localparam FLAG_Z = 1;
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localparam FLAG_S = 0;
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reg[1:0] flags;
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always @(negedge clk, posedge rst) begin
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if (rst) begin
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flags <= 2'b0;
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end else if (load_a) begin
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flags[FLAG_Z] <= (a == 0) ? 1'b1 : 1'b0;
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flags[FLAG_S] <= (a[7] == 1) ? 1'b1 : 1'b0;
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end else if (load_b) begin
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flags[FLAG_Z] <= (b == 0) ? 1'b1 : 1'b0;
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flags[FLAG_S] <= (b[7] == 1) ? 1'b1 : 1'b0;
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end else if (load_c) begin
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flags[FLAG_Z] <= (c == 0) ? 1'b1 : 1'b0;
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flags[FLAG_S] <= (c[7] == 1) ? 1'b1 : 1'b0;
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end
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end
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assign out = flags;
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endmodule
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