29 lines
383 B
Verilog
29 lines
383 B
Verilog
module register(
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input clk,
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input rst,
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input load,
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input inc,
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input dec,
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input[15:0] bus,
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output[7:0] out
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);
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reg[7:0] data;
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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data <= 8'b0;
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end else if (load) begin
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data <= bus[7:0];
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end else if (inc) begin
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data <= data + 1;
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end else if (dec) begin
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data <= data - 1;
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end
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end
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assign out = data;
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endmodule
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