PPU (inaccurate)
This commit is contained in:
parent
f2810585e4
commit
b1265da7d3
GPG Key ID:
FD6B27654AF5E348
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@ -10,9 +10,14 @@ add_executable(nes)
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target_sources(
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nes
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PRIVATE
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Source/Cartridge.cpp
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Source/CPU/CPU.cpp
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Source/CPU/AddressModes.cpp
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Source/CPU/Instructions.cpp
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Source/NES.cpp
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Source/Platform.cpp
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Source/PPU/PPU.cpp
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Source/PPU/Registers.hpp
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Source/Main.cpp)
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target_compile_options(
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@ -1,4 +1,5 @@
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#include "CPU.hpp"
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#include "NES.hpp"
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void CPU::Implicit()
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@ -14,56 +15,56 @@ void CPU::Immediate()
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pc += 2;
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fetchedAddress = pc - 1;
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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}
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void CPU::ZeroPage()
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{
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pc += 2;
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fetchedAddress = ReadMemory(pc - 1);
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedAddress = nes->Read(BusSource::CPU, pc - 1);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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}
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void CPU::ZeroPageX()
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{
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pc += 2;
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uint8_t operand = ReadMemory(pc - 1);
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uint8_t operand = nes->Read(BusSource::CPU, pc - 1);
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fetchedAddress = (operand + x) & 0xFFu;
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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}
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void CPU::ZeroPageY()
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{
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pc += 2;
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uint8_t operand = ReadMemory(pc - 1);
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uint8_t operand = nes->Read(BusSource::CPU, pc - 1);
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fetchedAddress = (operand + y) & 0xFFu;
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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}
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void CPU::Absolute()
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{
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pc += 3;
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uint8_t addressLsb = ReadMemory(pc - 2);
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uint8_t addressMsb = ReadMemory(pc - 1);
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uint8_t addressLsb = nes->Read(BusSource::CPU, pc - 2);
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uint8_t addressMsb = nes->Read(BusSource::CPU, pc - 1);
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fetchedAddress = ComposeAddress(addressMsb, addressLsb);
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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}
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void CPU::AbsoluteX()
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{
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pc += 3;
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uint8_t addressLsb = ReadMemory(pc - 2);
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uint8_t addressMsb = ReadMemory(pc - 1);
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uint8_t addressLsb = nes->Read(BusSource::CPU, pc - 2);
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uint8_t addressMsb = nes->Read(BusSource::CPU, pc - 1);
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uint16_t preAddress = ComposeAddress(addressMsb, addressLsb);
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fetchedAddress = preAddress + x;
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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pageBoundaryCrossed = IsPageBoundaryCrossed(preAddress, fetchedAddress);
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}
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@ -72,12 +73,12 @@ void CPU::AbsoluteY()
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{
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pc += 3;
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uint8_t addressLsb = ReadMemory(pc - 2);
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uint8_t addressMsb = ReadMemory(pc - 1);
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uint8_t addressLsb = nes->Read(BusSource::CPU, pc - 2);
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uint8_t addressMsb = nes->Read(BusSource::CPU, pc - 1);
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uint16_t preAddress = ComposeAddress(addressMsb, addressLsb);
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fetchedAddress = preAddress + y;
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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pageBoundaryCrossed = IsPageBoundaryCrossed(preAddress, fetchedAddress);
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}
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@ -86,52 +87,52 @@ void CPU::Indirect()
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{
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pc += 3;
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uint8_t indirectLsb = ReadMemory(pc - 2);
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uint8_t indirectMsb = ReadMemory(pc - 1);
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uint8_t indirectLsb = nes->Read(BusSource::CPU, pc - 2);
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uint8_t indirectMsb = nes->Read(BusSource::CPU, pc - 1);
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// NOTE: 6502 BUG - indirect address wraps
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// $02FF + 1 = $0200
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uint16_t addressIndirect = ComposeAddress(indirectMsb, indirectLsb);
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uint8_t addressLsb = ReadMemory(addressIndirect);
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uint8_t addressLsb = nes->Read(BusSource::CPU, addressIndirect);
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// Increment LSB to read second byte - it will wrap
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++indirectLsb;
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addressIndirect = ComposeAddress(indirectMsb, indirectLsb);
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uint8_t addressMsb = ReadMemory(addressIndirect);
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uint8_t addressMsb = nes->Read(BusSource::CPU, addressIndirect);
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fetchedAddress = ComposeAddress(addressMsb, addressLsb);
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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}
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void CPU::IndirectX()
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{
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pc += 2;
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uint8_t addressIndirect = ReadMemory(pc - 1) + x;
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uint8_t addressIndirect = nes->Read(BusSource::CPU, pc - 1) + x;
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// Modulo to keep within zero-page
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uint16_t addressLsb = ReadMemory((addressIndirect % 0x100));
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uint16_t addressMsb = ReadMemory((addressIndirect + 1) % 0x100);
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uint16_t addressLsb = nes->Read(BusSource::CPU, (addressIndirect % 0x100));
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uint16_t addressMsb = nes->Read(BusSource::CPU, (addressIndirect + 1) % 0x100);
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fetchedAddress = ComposeAddress(addressMsb, addressLsb);
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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}
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void CPU::IndirectY()
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{
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pc += 2;
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uint8_t addressIndirect = ReadMemory(pc - 1);
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uint8_t addressIndirect = nes->Read(BusSource::CPU, pc - 1);
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// Modulo to keep within zero-page
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uint8_t addressLsb = ReadMemory(addressIndirect % 0x100);
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uint8_t addressMsb = ReadMemory((addressIndirect + 1) % 0x100);
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uint8_t addressLsb = nes->Read(BusSource::CPU, addressIndirect % 0x100);
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uint8_t addressMsb = nes->Read(BusSource::CPU, (addressIndirect + 1) % 0x100);
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uint16_t preAddress = ComposeAddress(addressMsb, addressLsb);
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fetchedAddress = preAddress + y;
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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pageBoundaryCrossed = IsPageBoundaryCrossed(preAddress, fetchedAddress);
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}
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@ -140,12 +141,12 @@ void CPU::Relative()
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{
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pc += 2;
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int8_t operand = ReadMemory(pc - 1);
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int8_t operand = nes->Read(BusSource::CPU, pc - 1);
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uint16_t oldPc = pc;
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fetchedAddress = pc + operand;
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fetchedByte = ReadMemory(fetchedAddress);
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fetchedByte = nes->Read(BusSource::CPU, fetchedAddress);
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pageBoundaryCrossed = IsPageBoundaryCrossed(oldPc, fetchedAddress);
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}
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@ -1,314 +1,333 @@
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#include <iostream>
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#include <cstring>
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#include "CPU.hpp"
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#include "NES.hpp"
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const unsigned int STACK_START_ADDRESS = 0x100u;
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const unsigned int NMI_VECTOR_LSB = 0xFFFAu;
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const unsigned int NMI_VECTOR_MSB = 0xFFFBu;
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const unsigned int RESET_VECTOR_LSB = 0xFFFCu;
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const unsigned int RESET_VECTOR_MSB = 0xFFFDu;
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CPU::CPU()
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{
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status.SetByte(0x24);
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instructions[0xA9] = Instruction{.cycles = 2, .execute = &CPU::LDA, .fetch = &CPU::Immediate};
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instructions[0xA5] = Instruction{.cycles = 3, .execute = &CPU::LDA, .fetch = &CPU::ZeroPage};
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instructions[0xB5] = Instruction{.cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::ZeroPageX};
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instructions[0xAD] = Instruction{.cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::Absolute};
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instructions[0xBD] = Instruction{.cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::AbsoluteX};
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instructions[0xB9] = Instruction{.cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::AbsoluteY};
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instructions[0xA1] = Instruction{.cycles = 6, .execute = &CPU::LDA, .fetch = &CPU::IndirectX};
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instructions[0xB1] = Instruction{.cycles = 5, .execute = &CPU::LDA, .fetch = &CPU::IndirectY};
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instructions[0xA9] = Instruction{.name = "LDA", .cycles = 2, .execute = &CPU::LDA, .fetch = &CPU::Immediate};
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instructions[0xA5] = Instruction{.name = "LDA", .cycles = 3, .execute = &CPU::LDA, .fetch = &CPU::ZeroPage};
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instructions[0xB5] = Instruction{.name = "LDA", .cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::ZeroPageX};
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instructions[0xAD] = Instruction{.name = "LDA", .cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::Absolute};
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instructions[0xBD] = Instruction{.name = "LDA", .cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::AbsoluteX};
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instructions[0xB9] = Instruction{.name = "LDA", .cycles = 4, .execute = &CPU::LDA, .fetch = &CPU::AbsoluteY};
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instructions[0xA1] = Instruction{.name = "LDA", .cycles = 6, .execute = &CPU::LDA, .fetch = &CPU::IndirectX};
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instructions[0xB1] = Instruction{.name = "LDA", .cycles = 5, .execute = &CPU::LDA, .fetch = &CPU::IndirectY};
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instructions[0xA2] = Instruction{.cycles = 2, .execute = &CPU::LDX, .fetch = &CPU::Immediate};
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instructions[0xA6] = Instruction{.cycles = 3, .execute = &CPU::LDX, .fetch = &CPU::ZeroPage};
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instructions[0xB6] = Instruction{.cycles = 4, .execute = &CPU::LDX, .fetch = &CPU::ZeroPageY};
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instructions[0xAE] = Instruction{.cycles = 4, .execute = &CPU::LDX, .fetch = &CPU::Absolute};
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instructions[0xBE] = Instruction{.cycles = 4, .execute = &CPU::LDX, .fetch = &CPU::AbsoluteY};
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instructions[0xA2] = Instruction{.name = "LDX", .cycles = 2, .execute = &CPU::LDX, .fetch = &CPU::Immediate};
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instructions[0xA6] = Instruction{.name = "LDX", .cycles = 3, .execute = &CPU::LDX, .fetch = &CPU::ZeroPage};
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instructions[0xB6] = Instruction{.name = "LDX", .cycles = 4, .execute = &CPU::LDX, .fetch = &CPU::ZeroPageY};
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instructions[0xAE] = Instruction{.name = "LDX", .cycles = 4, .execute = &CPU::LDX, .fetch = &CPU::Absolute};
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instructions[0xBE] = Instruction{.name = "LDX", .cycles = 4, .execute = &CPU::LDX, .fetch = &CPU::AbsoluteY};
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instructions[0xA0] = Instruction{.cycles = 2, .execute = &CPU::LDY, .fetch = &CPU::Immediate};
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instructions[0xA4] = Instruction{.cycles = 3, .execute = &CPU::LDY, .fetch = &CPU::ZeroPage};
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instructions[0xB4] = Instruction{.cycles = 4, .execute = &CPU::LDY, .fetch = &CPU::ZeroPageX};
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instructions[0xAC] = Instruction{.cycles = 4, .execute = &CPU::LDY, .fetch = &CPU::Absolute};
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instructions[0xBC] = Instruction{.cycles = 4, .execute = &CPU::LDY, .fetch = &CPU::AbsoluteX};
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instructions[0xA0] = Instruction{.name = "LDY", .cycles = 2, .execute = &CPU::LDY, .fetch = &CPU::Immediate};
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instructions[0xA4] = Instruction{.name = "LDY", .cycles = 3, .execute = &CPU::LDY, .fetch = &CPU::ZeroPage};
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instructions[0xB4] = Instruction{.name = "LDY", .cycles = 4, .execute = &CPU::LDY, .fetch = &CPU::ZeroPageX};
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instructions[0xAC] = Instruction{.name = "LDY", .cycles = 4, .execute = &CPU::LDY, .fetch = &CPU::Absolute};
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instructions[0xBC] = Instruction{.name = "LDY", .cycles = 4, .execute = &CPU::LDY, .fetch = &CPU::AbsoluteX};
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instructions[0x85] = Instruction{.cycles = 3, .execute = &CPU::STA, .fetch = &CPU::ZeroPage};
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instructions[0x95] = Instruction{.cycles = 4, .execute = &CPU::STA, .fetch = &CPU::ZeroPageX};
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instructions[0x8D] = Instruction{.cycles = 4, .execute = &CPU::STA, .fetch = &CPU::Absolute};
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instructions[0x9D] = Instruction{.cycles = 5, .execute = &CPU::STA, .fetch = &CPU::AbsoluteX};
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instructions[0x99] = Instruction{.cycles = 5, .execute = &CPU::STA, .fetch = &CPU::AbsoluteY};
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instructions[0x81] = Instruction{.cycles = 6, .execute = &CPU::STA, .fetch = &CPU::IndirectX};
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instructions[0x91] = Instruction{.cycles = 6, .execute = &CPU::STA, .fetch = &CPU::IndirectY};
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instructions[0x85] = Instruction{.name = "STA", .cycles = 3, .execute = &CPU::STA, .fetch = &CPU::ZeroPage};
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instructions[0x95] = Instruction{.name = "STA", .cycles = 4, .execute = &CPU::STA, .fetch = &CPU::ZeroPageX};
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instructions[0x8D] = Instruction{.name = "STA", .cycles = 4, .execute = &CPU::STA, .fetch = &CPU::Absolute};
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instructions[0x9D] = Instruction{.name = "STA", .cycles = 5, .execute = &CPU::STA, .fetch = &CPU::AbsoluteX};
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instructions[0x99] = Instruction{.name = "STA", .cycles = 5, .execute = &CPU::STA, .fetch = &CPU::AbsoluteY};
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instructions[0x81] = Instruction{.name = "STA", .cycles = 6, .execute = &CPU::STA, .fetch = &CPU::IndirectX};
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instructions[0x91] = Instruction{.name = "STA", .cycles = 6, .execute = &CPU::STA, .fetch = &CPU::IndirectY};
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instructions[0x86] = Instruction{.cycles = 3, .execute = &CPU::STX, .fetch = &CPU::ZeroPage};
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instructions[0x96] = Instruction{.cycles = 4, .execute = &CPU::STX, .fetch = &CPU::ZeroPageY};
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instructions[0x8E] = Instruction{.cycles = 4, .execute = &CPU::STX, .fetch = &CPU::Absolute};
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instructions[0x86] = Instruction{.name = "STX", .cycles = 3, .execute = &CPU::STX, .fetch = &CPU::ZeroPage};
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instructions[0x96] = Instruction{.name = "STX", .cycles = 4, .execute = &CPU::STX, .fetch = &CPU::ZeroPageY};
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instructions[0x8E] = Instruction{.name = "STX", .cycles = 4, .execute = &CPU::STX, .fetch = &CPU::Absolute};
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instructions[0x84] = Instruction{.cycles = 3, .execute = &CPU::STY, .fetch = &CPU::ZeroPage};
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instructions[0x94] = Instruction{.cycles = 4, .execute = &CPU::STY, .fetch = &CPU::ZeroPageX};
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instructions[0x8C] = Instruction{.cycles = 4, .execute = &CPU::STY, .fetch = &CPU::Absolute};
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instructions[0x84] = Instruction{.name = "STY", .cycles = 3, .execute = &CPU::STY, .fetch = &CPU::ZeroPage};
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instructions[0x94] = Instruction{.name = "STY", .cycles = 4, .execute = &CPU::STY, .fetch = &CPU::ZeroPageX};
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instructions[0x8C] = Instruction{.name = "STY", .cycles = 4, .execute = &CPU::STY, .fetch = &CPU::Absolute};
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instructions[0xAA] = Instruction{.cycles = 2, .execute = &CPU::TAX, .fetch = &CPU::Implicit};
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instructions[0xA8] = Instruction{.cycles = 2, .execute = &CPU::TAY, .fetch = &CPU::Implicit};
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instructions[0x8A] = Instruction{.cycles = 2, .execute = &CPU::TXA, .fetch = &CPU::Implicit};
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instructions[0x98] = Instruction{.cycles = 2, .execute = &CPU::TYA, .fetch = &CPU::Implicit};
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instructions[0xBA] = Instruction{.cycles = 2, .execute = &CPU::TSX, .fetch = &CPU::Implicit};
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instructions[0x9A] = Instruction{.cycles = 2, .execute = &CPU::TXS, .fetch = &CPU::Implicit};
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instructions[0xAA] = Instruction{.name = "TAX", .cycles = 2, .execute = &CPU::TAX, .fetch = &CPU::Implicit};
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instructions[0xA8] = Instruction{.name = "TAY", .cycles = 2, .execute = &CPU::TAY, .fetch = &CPU::Implicit};
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instructions[0x8A] = Instruction{.name = "TXA", .cycles = 2, .execute = &CPU::TXA, .fetch = &CPU::Implicit};
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instructions[0x98] = Instruction{.name = "TYA", .cycles = 2, .execute = &CPU::TYA, .fetch = &CPU::Implicit};
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instructions[0xBA] = Instruction{.name = "TSX", .cycles = 2, .execute = &CPU::TSX, .fetch = &CPU::Implicit};
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instructions[0x9A] = Instruction{.name = "TXS", .cycles = 2, .execute = &CPU::TXS, .fetch = &CPU::Implicit};
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instructions[0x48] = Instruction{.cycles = 3, .execute = &CPU::PHA, .fetch = &CPU::Implicit};
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instructions[0x08] = Instruction{.cycles = 3, .execute = &CPU::PHP, .fetch = &CPU::Implicit};
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instructions[0x68] = Instruction{.cycles = 4, .execute = &CPU::PLA, .fetch = &CPU::Implicit};
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instructions[0x28] = Instruction{.cycles = 4, .execute = &CPU::PLP, .fetch = &CPU::Implicit};
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instructions[0x48] = Instruction{.name = "PHA", .cycles = 3, .execute = &CPU::PHA, .fetch = &CPU::Implicit};
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instructions[0x08] = Instruction{.name = "PHP", .cycles = 3, .execute = &CPU::PHP, .fetch = &CPU::Implicit};
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instructions[0x68] = Instruction{.name = "PLA", .cycles = 4, .execute = &CPU::PLA, .fetch = &CPU::Implicit};
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instructions[0x28] = Instruction{.name = "PLP", .cycles = 4, .execute = &CPU::PLP, .fetch = &CPU::Implicit};
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instructions[0x29] = Instruction{.cycles = 2, .execute = &CPU::AND, .fetch = &CPU::Immediate};
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instructions[0x25] = Instruction{.cycles = 3, .execute = &CPU::AND, .fetch = &CPU::ZeroPage};
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instructions[0x35] = Instruction{.cycles = 4, .execute = &CPU::AND, .fetch = &CPU::ZeroPageX};
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instructions[0x2D] = Instruction{.cycles = 4, .execute = &CPU::AND, .fetch = &CPU::Absolute};
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instructions[0x3D] = Instruction{.cycles = 4, .execute = &CPU::AND, .fetch = &CPU::AbsoluteX};
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instructions[0x39] = Instruction{.cycles = 4, .execute = &CPU::AND, .fetch = &CPU::AbsoluteY};
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instructions[0x21] = Instruction{.cycles = 6, .execute = &CPU::AND, .fetch = &CPU::IndirectX};
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instructions[0x31] = Instruction{.cycles = 5, .execute = &CPU::AND, .fetch = &CPU::IndirectY};
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instructions[0x29] = Instruction{.name = "AND", .cycles = 2, .execute = &CPU::AND, .fetch = &CPU::Immediate};
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instructions[0x25] = Instruction{.name = "AND", .cycles = 3, .execute = &CPU::AND, .fetch = &CPU::ZeroPage};
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instructions[0x35] = Instruction{.name = "AND", .cycles = 4, .execute = &CPU::AND, .fetch = &CPU::ZeroPageX};
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instructions[0x2D] = Instruction{.name = "AND", .cycles = 4, .execute = &CPU::AND, .fetch = &CPU::Absolute};
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instructions[0x3D] = Instruction{.name = "AND", .cycles = 4, .execute = &CPU::AND, .fetch = &CPU::AbsoluteX};
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instructions[0x39] = Instruction{.name = "AND", .cycles = 4, .execute = &CPU::AND, .fetch = &CPU::AbsoluteY};
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instructions[0x21] = Instruction{.name = "AND", .cycles = 6, .execute = &CPU::AND, .fetch = &CPU::IndirectX};
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instructions[0x31] = Instruction{.name = "AND", .cycles = 5, .execute = &CPU::AND, .fetch = &CPU::IndirectY};
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|
||||
instructions[0x49] = Instruction{.cycles = 2, .execute = &CPU::EOR, .fetch = &CPU::Immediate};
|
||||
instructions[0x45] = Instruction{.cycles = 3, .execute = &CPU::EOR, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x55] = Instruction{.cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x4D] = Instruction{.cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::Absolute};
|
||||
instructions[0x5D] = Instruction{.cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x59] = Instruction{.cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x41] = Instruction{.cycles = 6, .execute = &CPU::EOR, .fetch = &CPU::IndirectX};
|
||||
instructions[0x51] = Instruction{.cycles = 5, .execute = &CPU::EOR, .fetch = &CPU::IndirectY};
|
||||
instructions[0x49] = Instruction{.name = "EOR", .cycles = 2, .execute = &CPU::EOR, .fetch = &CPU::Immediate};
|
||||
instructions[0x45] = Instruction{.name = "EOR", .cycles = 3, .execute = &CPU::EOR, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x55] = Instruction{.name = "EOR", .cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x4D] = Instruction{.name = "EOR", .cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::Absolute};
|
||||
instructions[0x5D] = Instruction{.name = "EOR", .cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x59] = Instruction{.name = "EOR", .cycles = 4, .execute = &CPU::EOR, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x41] = Instruction{.name = "EOR", .cycles = 6, .execute = &CPU::EOR, .fetch = &CPU::IndirectX};
|
||||
instructions[0x51] = Instruction{.name = "EOR", .cycles = 5, .execute = &CPU::EOR, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0x09] = Instruction{.cycles = 2, .execute = &CPU::ORA, .fetch = &CPU::Immediate};
|
||||
instructions[0x05] = Instruction{.cycles = 3, .execute = &CPU::ORA, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x15] = Instruction{.cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0D] = Instruction{.cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::Absolute};
|
||||
instructions[0x1D] = Instruction{.cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x19] = Instruction{.cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x01] = Instruction{.cycles = 6, .execute = &CPU::ORA, .fetch = &CPU::IndirectX};
|
||||
instructions[0x11] = Instruction{.cycles = 5, .execute = &CPU::ORA, .fetch = &CPU::IndirectY};
|
||||
instructions[0x09] = Instruction{.name = "ORA", .cycles = 2, .execute = &CPU::ORA, .fetch = &CPU::Immediate};
|
||||
instructions[0x05] = Instruction{.name = "ORA", .cycles = 3, .execute = &CPU::ORA, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x15] = Instruction{.name = "ORA", .cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0D] = Instruction{.name = "ORA", .cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::Absolute};
|
||||
instructions[0x1D] = Instruction{.name = "ORA", .cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x19] = Instruction{.name = "ORA", .cycles = 4, .execute = &CPU::ORA, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x01] = Instruction{.name = "ORA", .cycles = 6, .execute = &CPU::ORA, .fetch = &CPU::IndirectX};
|
||||
instructions[0x11] = Instruction{.name = "ORA", .cycles = 5, .execute = &CPU::ORA, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0x24] = Instruction{.cycles = 3, .execute = &CPU::BIT, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x2C] = Instruction{.cycles = 4, .execute = &CPU::BIT, .fetch = &CPU::Absolute};
|
||||
instructions[0x24] = Instruction{.name = "BIT", .cycles = 3, .execute = &CPU::BIT, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x2C] = Instruction{.name = "BIT", .cycles = 4, .execute = &CPU::BIT, .fetch = &CPU::Absolute};
|
||||
|
||||
instructions[0x69] = Instruction{.cycles = 2, .execute = &CPU::ADC, .fetch = &CPU::Immediate};
|
||||
instructions[0x65] = Instruction{.cycles = 3, .execute = &CPU::ADC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x75] = Instruction{.cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x6D] = Instruction{.cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::Absolute};
|
||||
instructions[0x7D] = Instruction{.cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x79] = Instruction{.cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x61] = Instruction{.cycles = 6, .execute = &CPU::ADC, .fetch = &CPU::IndirectX};
|
||||
instructions[0x71] = Instruction{.cycles = 5, .execute = &CPU::ADC, .fetch = &CPU::IndirectY};
|
||||
instructions[0x69] = Instruction{.name = "ADC", .cycles = 2, .execute = &CPU::ADC, .fetch = &CPU::Immediate};
|
||||
instructions[0x65] = Instruction{.name = "ADC", .cycles = 3, .execute = &CPU::ADC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x75] = Instruction{.name = "ADC", .cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x6D] = Instruction{.name = "ADC", .cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::Absolute};
|
||||
instructions[0x7D] = Instruction{.name = "ADC", .cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x79] = Instruction{.name = "ADC", .cycles = 4, .execute = &CPU::ADC, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x61] = Instruction{.name = "ADC", .cycles = 6, .execute = &CPU::ADC, .fetch = &CPU::IndirectX};
|
||||
instructions[0x71] = Instruction{.name = "ADC", .cycles = 5, .execute = &CPU::ADC, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0xE9] = Instruction{.cycles = 2, .execute = &CPU::SBC, .fetch = &CPU::Immediate};
|
||||
instructions[0xE5] = Instruction{.cycles = 3, .execute = &CPU::SBC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xF5] = Instruction{.cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xED] = Instruction{.cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::Absolute};
|
||||
instructions[0xFD] = Instruction{.cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xF9] = Instruction{.cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xE1] = Instruction{.cycles = 6, .execute = &CPU::SBC, .fetch = &CPU::IndirectX};
|
||||
instructions[0xF1] = Instruction{.cycles = 5, .execute = &CPU::SBC, .fetch = &CPU::IndirectY};
|
||||
instructions[0xE9] = Instruction{.name = "SBC", .cycles = 2, .execute = &CPU::SBC, .fetch = &CPU::Immediate};
|
||||
instructions[0xE5] = Instruction{.name = "SBC", .cycles = 3, .execute = &CPU::SBC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xF5] = Instruction{.name = "SBC", .cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xED] = Instruction{.name = "SBC", .cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::Absolute};
|
||||
instructions[0xFD] = Instruction{.name = "SBC", .cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xF9] = Instruction{.name = "SBC", .cycles = 4, .execute = &CPU::SBC, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xE1] = Instruction{.name = "SBC", .cycles = 6, .execute = &CPU::SBC, .fetch = &CPU::IndirectX};
|
||||
instructions[0xF1] = Instruction{.name = "SBC", .cycles = 5, .execute = &CPU::SBC, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0xC9] = Instruction{.cycles = 2, .execute = &CPU::CMP, .fetch = &CPU::Immediate};
|
||||
instructions[0xC5] = Instruction{.cycles = 3, .execute = &CPU::CMP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xD5] = Instruction{.cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xCD] = Instruction{.cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::Absolute};
|
||||
instructions[0xDD] = Instruction{.cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xD9] = Instruction{.cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xC1] = Instruction{.cycles = 6, .execute = &CPU::CMP, .fetch = &CPU::IndirectX};
|
||||
instructions[0xD1] = Instruction{.cycles = 5, .execute = &CPU::CMP, .fetch = &CPU::IndirectY};
|
||||
instructions[0xC9] = Instruction{.name = "CMP", .cycles = 2, .execute = &CPU::CMP, .fetch = &CPU::Immediate};
|
||||
instructions[0xC5] = Instruction{.name = "CMP", .cycles = 3, .execute = &CPU::CMP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xD5] = Instruction{.name = "CMP", .cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xCD] = Instruction{.name = "CMP", .cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::Absolute};
|
||||
instructions[0xDD] = Instruction{.name = "CMP", .cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xD9] = Instruction{.name = "CMP", .cycles = 4, .execute = &CPU::CMP, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xC1] = Instruction{.name = "CMP", .cycles = 6, .execute = &CPU::CMP, .fetch = &CPU::IndirectX};
|
||||
instructions[0xD1] = Instruction{.name = "CMP", .cycles = 5, .execute = &CPU::CMP, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0xE0] = Instruction{.cycles = 2, .execute = &CPU::CPX, .fetch = &CPU::Immediate};
|
||||
instructions[0xE4] = Instruction{.cycles = 3, .execute = &CPU::CPX, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xEC] = Instruction{.cycles = 4, .execute = &CPU::CPX, .fetch = &CPU::Absolute};
|
||||
instructions[0xE0] = Instruction{.name = "CPX", .cycles = 2, .execute = &CPU::CPX, .fetch = &CPU::Immediate};
|
||||
instructions[0xE4] = Instruction{.name = "CPX", .cycles = 3, .execute = &CPU::CPX, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xEC] = Instruction{.name = "CPX", .cycles = 4, .execute = &CPU::CPX, .fetch = &CPU::Absolute};
|
||||
|
||||
instructions[0xC0] = Instruction{.cycles = 2, .execute = &CPU::CPY, .fetch = &CPU::Immediate};
|
||||
instructions[0xC4] = Instruction{.cycles = 3, .execute = &CPU::CPY, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xCC] = Instruction{.cycles = 4, .execute = &CPU::CPY, .fetch = &CPU::Absolute};
|
||||
instructions[0xC0] = Instruction{.name = "CPY", .cycles = 2, .execute = &CPU::CPY, .fetch = &CPU::Immediate};
|
||||
instructions[0xC4] = Instruction{.name = "CPY", .cycles = 3, .execute = &CPU::CPY, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xCC] = Instruction{.name = "CPY", .cycles = 4, .execute = &CPU::CPY, .fetch = &CPU::Absolute};
|
||||
|
||||
instructions[0xE6] = Instruction{.cycles = 5, .execute = &CPU::INC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xF6] = Instruction{.cycles = 6, .execute = &CPU::INC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xEE] = Instruction{.cycles = 6, .execute = &CPU::INC, .fetch = &CPU::Absolute};
|
||||
instructions[0xFE] = Instruction{.cycles = 7, .execute = &CPU::INC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xE6] = Instruction{.name = "INC", .cycles = 5, .execute = &CPU::INC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xF6] = Instruction{.name = "INC", .cycles = 6, .execute = &CPU::INC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xEE] = Instruction{.name = "INC", .cycles = 6, .execute = &CPU::INC, .fetch = &CPU::Absolute};
|
||||
instructions[0xFE] = Instruction{.name = "INC", .cycles = 7, .execute = &CPU::INC, .fetch = &CPU::AbsoluteX};
|
||||
|
||||
instructions[0xE8] = Instruction{.cycles = 2, .execute = &CPU::INX, .fetch = &CPU::Implicit};
|
||||
instructions[0xE8] = Instruction{.name = "INX", .cycles = 2, .execute = &CPU::INX, .fetch = &CPU::Implicit};
|
||||
|
||||
instructions[0xC8] = Instruction{.cycles = 2, .execute = &CPU::INY, .fetch = &CPU::Implicit};
|
||||
instructions[0xC8] = Instruction{.name = "INY", .cycles = 2, .execute = &CPU::INY, .fetch = &CPU::Implicit};
|
||||
|
||||
instructions[0xC6] = Instruction{.cycles = 5, .execute = &CPU::DEC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xD6] = Instruction{.cycles = 6, .execute = &CPU::DEC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xCE] = Instruction{.cycles = 6, .execute = &CPU::DEC, .fetch = &CPU::Absolute};
|
||||
instructions[0xDE] = Instruction{.cycles = 7, .execute = &CPU::DEC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xC6] = Instruction{.name = "DEC", .cycles = 5, .execute = &CPU::DEC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xD6] = Instruction{.name = "DEC", .cycles = 6, .execute = &CPU::DEC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xCE] = Instruction{.name = "DEC", .cycles = 6, .execute = &CPU::DEC, .fetch = &CPU::Absolute};
|
||||
instructions[0xDE] = Instruction{.name = "DEC", .cycles = 7, .execute = &CPU::DEC, .fetch = &CPU::AbsoluteX};
|
||||
|
||||
instructions[0xCA] = Instruction{.cycles = 2, .execute = &CPU::DEX, .fetch = &CPU::Implicit};
|
||||
instructions[0xCA] = Instruction{.name = "DEX", .cycles = 2, .execute = &CPU::DEX, .fetch = &CPU::Implicit};
|
||||
|
||||
instructions[0x88] = Instruction{.cycles = 2, .execute = &CPU::DEY, .fetch = &CPU::Implicit};
|
||||
instructions[0x88] = Instruction{.name = "DEY", .cycles = 2, .execute = &CPU::DEY, .fetch = &CPU::Implicit};
|
||||
|
||||
instructions[0x0A] = Instruction{.cycles = 2, .execute = &CPU::ASL, .fetch = &CPU::Implicit};
|
||||
instructions[0x06] = Instruction{.cycles = 5, .execute = &CPU::ASL, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x16] = Instruction{.cycles = 6, .execute = &CPU::ASL, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0E] = Instruction{.cycles = 6, .execute = &CPU::ASL, .fetch = &CPU::Absolute};
|
||||
instructions[0x1E] = Instruction{.cycles = 7, .execute = &CPU::ASL, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x0A] = Instruction{.name = "ASL", .cycles = 2, .execute = &CPU::ASL, .fetch = &CPU::Implicit};
|
||||
instructions[0x06] = Instruction{.name = "ASL", .cycles = 5, .execute = &CPU::ASL, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x16] = Instruction{.name = "ASL", .cycles = 6, .execute = &CPU::ASL, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0E] = Instruction{.name = "ASL", .cycles = 6, .execute = &CPU::ASL, .fetch = &CPU::Absolute};
|
||||
instructions[0x1E] = Instruction{.name = "ASL", .cycles = 7, .execute = &CPU::ASL, .fetch = &CPU::AbsoluteX};
|
||||
|
||||
instructions[0x4A] = Instruction{.cycles = 2, .execute = &CPU::LSR, .fetch = &CPU::Implicit};
|
||||
instructions[0x46] = Instruction{.cycles = 5, .execute = &CPU::LSR, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x56] = Instruction{.cycles = 6, .execute = &CPU::LSR, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x4E] = Instruction{.cycles = 6, .execute = &CPU::LSR, .fetch = &CPU::Absolute};
|
||||
instructions[0x5E] = Instruction{.cycles = 7, .execute = &CPU::LSR, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x4A] = Instruction{.name = "LSR", .cycles = 2, .execute = &CPU::LSR, .fetch = &CPU::Implicit};
|
||||
instructions[0x46] = Instruction{.name = "LSR", .cycles = 5, .execute = &CPU::LSR, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x56] = Instruction{.name = "LSR", .cycles = 6, .execute = &CPU::LSR, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x4E] = Instruction{.name = "LSR", .cycles = 6, .execute = &CPU::LSR, .fetch = &CPU::Absolute};
|
||||
instructions[0x5E] = Instruction{.name = "LSR", .cycles = 7, .execute = &CPU::LSR, .fetch = &CPU::AbsoluteX};
|
||||
|
||||
instructions[0x2A] = Instruction{.cycles = 2, .execute = &CPU::ROL, .fetch = &CPU::Implicit};
|
||||
instructions[0x26] = Instruction{.cycles = 5, .execute = &CPU::ROL, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x36] = Instruction{.cycles = 6, .execute = &CPU::ROL, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x2E] = Instruction{.cycles = 6, .execute = &CPU::ROL, .fetch = &CPU::Absolute};
|
||||
instructions[0x3E] = Instruction{.cycles = 7, .execute = &CPU::ROL, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x2A] = Instruction{.name = "ROL", .cycles = 2, .execute = &CPU::ROL, .fetch = &CPU::Implicit};
|
||||
instructions[0x26] = Instruction{.name = "ROL", .cycles = 5, .execute = &CPU::ROL, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x36] = Instruction{.name = "ROL", .cycles = 6, .execute = &CPU::ROL, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x2E] = Instruction{.name = "ROL", .cycles = 6, .execute = &CPU::ROL, .fetch = &CPU::Absolute};
|
||||
instructions[0x3E] = Instruction{.name = "ROL", .cycles = 7, .execute = &CPU::ROL, .fetch = &CPU::AbsoluteX};
|
||||
|
||||
instructions[0x6A] = Instruction{.cycles = 2, .execute = &CPU::ROR, .fetch = &CPU::Implicit};
|
||||
instructions[0x66] = Instruction{.cycles = 5, .execute = &CPU::ROR, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x76] = Instruction{.cycles = 6, .execute = &CPU::ROR, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x6E] = Instruction{.cycles = 6, .execute = &CPU::ROR, .fetch = &CPU::Absolute};
|
||||
instructions[0x7E] = Instruction{.cycles = 7, .execute = &CPU::ROR, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x6A] = Instruction{.name = "ROR", .cycles = 2, .execute = &CPU::ROR, .fetch = &CPU::Implicit};
|
||||
instructions[0x66] = Instruction{.name = "ROR", .cycles = 5, .execute = &CPU::ROR, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x76] = Instruction{.name = "ROR", .cycles = 6, .execute = &CPU::ROR, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x6E] = Instruction{.name = "ROR", .cycles = 6, .execute = &CPU::ROR, .fetch = &CPU::Absolute};
|
||||
instructions[0x7E] = Instruction{.name = "ROR", .cycles = 7, .execute = &CPU::ROR, .fetch = &CPU::AbsoluteX};
|
||||
|
||||
instructions[0x4C] = Instruction{.cycles = 3, .execute = &CPU::JMP, .fetch = &CPU::Absolute};
|
||||
instructions[0x6C] = Instruction{.cycles = 5, .execute = &CPU::JMP, .fetch = &CPU::Indirect};
|
||||
instructions[0x4C] = Instruction{.name = "JMP", .cycles = 3, .execute = &CPU::JMP, .fetch = &CPU::Absolute};
|
||||
instructions[0x6C] = Instruction{.name = "JMP", .cycles = 5, .execute = &CPU::JMP, .fetch = &CPU::Indirect};
|
||||
|
||||
instructions[0x20] = Instruction{.cycles = 6, .execute = &CPU::JSR, .fetch = &CPU::Absolute};
|
||||
instructions[0x20] = Instruction{.name = "JSR", .cycles = 6, .execute = &CPU::JSR, .fetch = &CPU::Absolute};
|
||||
|
||||
instructions[0x60] = Instruction{.cycles = 6, .execute = &CPU::RTS, .fetch = &CPU::Implicit};
|
||||
instructions[0x60] = Instruction{.name = "RTS", .cycles = 6, .execute = &CPU::RTS, .fetch = &CPU::Implicit};
|
||||
|
||||
instructions[0x90] = Instruction{.cycles = 2, .execute = &CPU::BCC, .fetch = &CPU::Relative};
|
||||
instructions[0xB0] = Instruction{.cycles = 2, .execute = &CPU::BCS, .fetch = &CPU::Relative};
|
||||
instructions[0xF0] = Instruction{.cycles = 2, .execute = &CPU::BEQ, .fetch = &CPU::Relative};
|
||||
instructions[0x30] = Instruction{.cycles = 2, .execute = &CPU::BMI, .fetch = &CPU::Relative};
|
||||
instructions[0xD0] = Instruction{.cycles = 2, .execute = &CPU::BNE, .fetch = &CPU::Relative};
|
||||
instructions[0x10] = Instruction{.cycles = 2, .execute = &CPU::BPL, .fetch = &CPU::Relative};
|
||||
instructions[0x50] = Instruction{.cycles = 2, .execute = &CPU::BVC, .fetch = &CPU::Relative};
|
||||
instructions[0x70] = Instruction{.cycles = 2, .execute = &CPU::BVS, .fetch = &CPU::Relative};
|
||||
instructions[0x90] = Instruction{.name = "BCC", .cycles = 2, .execute = &CPU::BCC, .fetch = &CPU::Relative};
|
||||
instructions[0xB0] = Instruction{.name = "BCS", .cycles = 2, .execute = &CPU::BCS, .fetch = &CPU::Relative};
|
||||
instructions[0xF0] = Instruction{.name = "BEQ", .cycles = 2, .execute = &CPU::BEQ, .fetch = &CPU::Relative};
|
||||
instructions[0x30] = Instruction{.name = "BMI", .cycles = 2, .execute = &CPU::BMI, .fetch = &CPU::Relative};
|
||||
instructions[0xD0] = Instruction{.name = "BNE", .cycles = 2, .execute = &CPU::BNE, .fetch = &CPU::Relative};
|
||||
instructions[0x10] = Instruction{.name = "BPL", .cycles = 2, .execute = &CPU::BPL, .fetch = &CPU::Relative};
|
||||
instructions[0x50] = Instruction{.name = "BVC", .cycles = 2, .execute = &CPU::BVC, .fetch = &CPU::Relative};
|
||||
instructions[0x70] = Instruction{.name = "BVS", .cycles = 2, .execute = &CPU::BVS, .fetch = &CPU::Relative};
|
||||
|
||||
instructions[0x18] = Instruction{.cycles = 2, .execute = &CPU::CLC, .fetch = &CPU::Implicit};
|
||||
instructions[0xD8] = Instruction{.cycles = 2, .execute = &CPU::CLD, .fetch = &CPU::Implicit};
|
||||
instructions[0x58] = Instruction{.cycles = 2, .execute = &CPU::CLI, .fetch = &CPU::Implicit};
|
||||
instructions[0xB8] = Instruction{.cycles = 2, .execute = &CPU::CLV, .fetch = &CPU::Implicit};
|
||||
instructions[0x38] = Instruction{.cycles = 2, .execute = &CPU::SEC, .fetch = &CPU::Implicit};
|
||||
instructions[0xF8] = Instruction{.cycles = 2, .execute = &CPU::SED, .fetch = &CPU::Implicit};
|
||||
instructions[0x78] = Instruction{.cycles = 2, .execute = &CPU::SEI, .fetch = &CPU::Implicit};
|
||||
instructions[0x18] = Instruction{.name = "CLC", .cycles = 2, .execute = &CPU::CLC, .fetch = &CPU::Implicit};
|
||||
instructions[0xD8] = Instruction{.name = "CLD", .cycles = 2, .execute = &CPU::CLD, .fetch = &CPU::Implicit};
|
||||
instructions[0x58] = Instruction{.name = "CLI", .cycles = 2, .execute = &CPU::CLI, .fetch = &CPU::Implicit};
|
||||
instructions[0xB8] = Instruction{.name = "CLV", .cycles = 2, .execute = &CPU::CLV, .fetch = &CPU::Implicit};
|
||||
instructions[0x38] = Instruction{.name = "SEC", .cycles = 2, .execute = &CPU::SEC, .fetch = &CPU::Implicit};
|
||||
instructions[0xF8] = Instruction{.name = "SED", .cycles = 2, .execute = &CPU::SED, .fetch = &CPU::Implicit};
|
||||
instructions[0x78] = Instruction{.name = "SEI", .cycles = 2, .execute = &CPU::SEI, .fetch = &CPU::Implicit};
|
||||
|
||||
instructions[0x00] = Instruction{.cycles = 7, .execute = &CPU::BRK, .fetch = &CPU::Implicit};
|
||||
instructions[0xEA] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x40] = Instruction{.cycles = 6, .execute = &CPU::RTI, .fetch = &CPU::Implicit};
|
||||
instructions[0x00] = Instruction{.name = "BRK", .cycles = 7, .execute = &CPU::BRK, .fetch = &CPU::Immediate};
|
||||
instructions[0xEA] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x40] = Instruction{.name = "RTI", .cycles = 6, .execute = &CPU::RTI, .fetch = &CPU::Implicit};
|
||||
|
||||
instructions[0x1A] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x3A] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x5A] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x7A] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xDA] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xFA] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x80] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0x82] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0x89] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0xC2] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0xE2] = Instruction{.cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0x04] = Instruction{.cycles = 3, .execute = &CPU::NOP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x44] = Instruction{.cycles = 3, .execute = &CPU::NOP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x64] = Instruction{.cycles = 3, .execute = &CPU::NOP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x14] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x34] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x54] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x74] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xD4] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xF4] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0C] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::Absolute};
|
||||
instructions[0x1C] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x3C] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x5C] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x7C] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xDC] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xFC] = Instruction{.cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x1A] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x3A] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x5A] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x7A] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xDA] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xFA] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x80] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0x82] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0x89] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0xC2] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0xE2] = Instruction{.name = "NOP", .cycles = 2, .execute = &CPU::NOP, .fetch = &CPU::Immediate};
|
||||
instructions[0x04] = Instruction{.name = "NOP", .cycles = 3, .execute = &CPU::NOP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x44] = Instruction{.name = "NOP", .cycles = 3, .execute = &CPU::NOP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x64] = Instruction{.name = "NOP", .cycles = 3, .execute = &CPU::NOP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x14] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x34] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x54] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x74] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xD4] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xF4] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0C] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::Absolute};
|
||||
instructions[0x1C] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x3C] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x5C] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x7C] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xDC] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xFC] = Instruction{.name = "NOP", .cycles = 4, .execute = &CPU::NOP, .fetch = &CPU::AbsoluteX};
|
||||
|
||||
instructions[0x07] = Instruction{.cycles = 5, .execute = &CPU::SLO, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x17] = Instruction{.cycles = 6, .execute = &CPU::SLO, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0F] = Instruction{.cycles = 6, .execute = &CPU::SLO, .fetch = &CPU::Absolute};
|
||||
instructions[0x1F] = Instruction{.cycles = 7, .execute = &CPU::SLO, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x1B] = Instruction{.cycles = 7, .execute = &CPU::SLO, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x03] = Instruction{.cycles = 8, .execute = &CPU::SLO, .fetch = &CPU::IndirectX};
|
||||
instructions[0x13] = Instruction{.cycles = 8, .execute = &CPU::SLO, .fetch = &CPU::IndirectY};
|
||||
instructions[0x07] = Instruction{.name = "SLO", .cycles = 5, .execute = &CPU::SLO, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x17] = Instruction{.name = "SLO", .cycles = 6, .execute = &CPU::SLO, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x0F] = Instruction{.name = "SLO", .cycles = 6, .execute = &CPU::SLO, .fetch = &CPU::Absolute};
|
||||
instructions[0x1F] = Instruction{.name = "SLO", .cycles = 7, .execute = &CPU::SLO, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x1B] = Instruction{.name = "SLO", .cycles = 7, .execute = &CPU::SLO, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x03] = Instruction{.name = "SLO", .cycles = 8, .execute = &CPU::SLO, .fetch = &CPU::IndirectX};
|
||||
instructions[0x13] = Instruction{.name = "SLO", .cycles = 8, .execute = &CPU::SLO, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0x27] = Instruction{.cycles = 5, .execute = &CPU::RLA, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x37] = Instruction{.cycles = 6, .execute = &CPU::RLA, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x2F] = Instruction{.cycles = 6, .execute = &CPU::RLA, .fetch = &CPU::Absolute};
|
||||
instructions[0x3F] = Instruction{.cycles = 7, .execute = &CPU::RLA, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x3B] = Instruction{.cycles = 7, .execute = &CPU::RLA, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x23] = Instruction{.cycles = 8, .execute = &CPU::RLA, .fetch = &CPU::IndirectX};
|
||||
instructions[0x33] = Instruction{.cycles = 8, .execute = &CPU::RLA, .fetch = &CPU::IndirectY};
|
||||
instructions[0x27] = Instruction{.name = "RLA", .cycles = 5, .execute = &CPU::RLA, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x37] = Instruction{.name = "RLA", .cycles = 6, .execute = &CPU::RLA, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x2F] = Instruction{.name = "RLA", .cycles = 6, .execute = &CPU::RLA, .fetch = &CPU::Absolute};
|
||||
instructions[0x3F] = Instruction{.name = "RLA", .cycles = 7, .execute = &CPU::RLA, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x3B] = Instruction{.name = "RLA", .cycles = 7, .execute = &CPU::RLA, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x23] = Instruction{.name = "RLA", .cycles = 8, .execute = &CPU::RLA, .fetch = &CPU::IndirectX};
|
||||
instructions[0x33] = Instruction{.name = "RLA", .cycles = 8, .execute = &CPU::RLA, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0x47] = Instruction{.cycles = 5, .execute = &CPU::SRE, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x57] = Instruction{.cycles = 6, .execute = &CPU::SRE, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x4F] = Instruction{.cycles = 6, .execute = &CPU::SRE, .fetch = &CPU::Absolute};
|
||||
instructions[0x5F] = Instruction{.cycles = 7, .execute = &CPU::SRE, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x5B] = Instruction{.cycles = 7, .execute = &CPU::SRE, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x43] = Instruction{.cycles = 8, .execute = &CPU::SRE, .fetch = &CPU::IndirectX};
|
||||
instructions[0x53] = Instruction{.cycles = 8, .execute = &CPU::SRE, .fetch = &CPU::IndirectY};
|
||||
instructions[0x47] = Instruction{.name = "SRE", .cycles = 5, .execute = &CPU::SRE, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x57] = Instruction{.name = "SRE", .cycles = 6, .execute = &CPU::SRE, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x4F] = Instruction{.name = "SRE", .cycles = 6, .execute = &CPU::SRE, .fetch = &CPU::Absolute};
|
||||
instructions[0x5F] = Instruction{.name = "SRE", .cycles = 7, .execute = &CPU::SRE, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x5B] = Instruction{.name = "SRE", .cycles = 7, .execute = &CPU::SRE, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x43] = Instruction{.name = "SRE", .cycles = 8, .execute = &CPU::SRE, .fetch = &CPU::IndirectX};
|
||||
instructions[0x53] = Instruction{.name = "SRE", .cycles = 8, .execute = &CPU::SRE, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0x67] = Instruction{.cycles = 5, .execute = &CPU::RRA, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x77] = Instruction{.cycles = 6, .execute = &CPU::RRA, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x6F] = Instruction{.cycles = 6, .execute = &CPU::RRA, .fetch = &CPU::Absolute};
|
||||
instructions[0x7F] = Instruction{.cycles = 7, .execute = &CPU::RRA, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x7B] = Instruction{.cycles = 7, .execute = &CPU::RRA, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x63] = Instruction{.cycles = 8, .execute = &CPU::RRA, .fetch = &CPU::IndirectX};
|
||||
instructions[0x73] = Instruction{.cycles = 8, .execute = &CPU::RRA, .fetch = &CPU::IndirectY};
|
||||
instructions[0x67] = Instruction{.name = "RRA", .cycles = 5, .execute = &CPU::RRA, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x77] = Instruction{.name = "RRA", .cycles = 6, .execute = &CPU::RRA, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0x6F] = Instruction{.name = "RRA", .cycles = 6, .execute = &CPU::RRA, .fetch = &CPU::Absolute};
|
||||
instructions[0x7F] = Instruction{.name = "RRA", .cycles = 7, .execute = &CPU::RRA, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0x7B] = Instruction{.name = "RRA", .cycles = 7, .execute = &CPU::RRA, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0x63] = Instruction{.name = "RRA", .cycles = 8, .execute = &CPU::RRA, .fetch = &CPU::IndirectX};
|
||||
instructions[0x73] = Instruction{.name = "RRA", .cycles = 8, .execute = &CPU::RRA, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0x87] = Instruction{.cycles = 3, .execute = &CPU::SAX, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x97] = Instruction{.cycles = 4, .execute = &CPU::SAX, .fetch = &CPU::ZeroPageY};
|
||||
instructions[0x8F] = Instruction{.cycles = 4, .execute = &CPU::SAX, .fetch = &CPU::Absolute};
|
||||
instructions[0x83] = Instruction{.cycles = 6, .execute = &CPU::SAX, .fetch = &CPU::IndirectX};
|
||||
instructions[0x87] = Instruction{.name = "SAX", .cycles = 3, .execute = &CPU::SAX, .fetch = &CPU::ZeroPage};
|
||||
instructions[0x97] = Instruction{.name = "SAX", .cycles = 4, .execute = &CPU::SAX, .fetch = &CPU::ZeroPageY};
|
||||
instructions[0x8F] = Instruction{.name = "SAX", .cycles = 4, .execute = &CPU::SAX, .fetch = &CPU::Absolute};
|
||||
instructions[0x83] = Instruction{.name = "SAX", .cycles = 6, .execute = &CPU::SAX, .fetch = &CPU::IndirectX};
|
||||
|
||||
instructions[0xEB] = Instruction{.cycles = 2, .execute = &CPU::SBC, .fetch = &CPU::Immediate};
|
||||
instructions[0xEB] = Instruction{.name = "SBC", .cycles = 2, .execute = &CPU::SBC, .fetch = &CPU::Immediate};
|
||||
|
||||
instructions[0xAB] = Instruction{.cycles = 2, .execute = &CPU::LAX, .fetch = &CPU::Immediate};
|
||||
instructions[0xA7] = Instruction{.cycles = 3, .execute = &CPU::LAX, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xB7] = Instruction{.cycles = 4, .execute = &CPU::LAX, .fetch = &CPU::ZeroPageY};
|
||||
instructions[0xAF] = Instruction{.cycles = 4, .execute = &CPU::LAX, .fetch = &CPU::Absolute};
|
||||
instructions[0xBF] = Instruction{.cycles = 4, .execute = &CPU::LAX, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xA3] = Instruction{.cycles = 6, .execute = &CPU::LAX, .fetch = &CPU::IndirectX};
|
||||
instructions[0xB3] = Instruction{.cycles = 5, .execute = &CPU::LAX, .fetch = &CPU::IndirectY};
|
||||
instructions[0xAB] = Instruction{.name = "LAX", .cycles = 2, .execute = &CPU::LAX, .fetch = &CPU::Immediate};
|
||||
instructions[0xA7] = Instruction{.name = "LAX", .cycles = 3, .execute = &CPU::LAX, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xB7] = Instruction{.name = "LAX", .cycles = 4, .execute = &CPU::LAX, .fetch = &CPU::ZeroPageY};
|
||||
instructions[0xAF] = Instruction{.name = "LAX", .cycles = 4, .execute = &CPU::LAX, .fetch = &CPU::Absolute};
|
||||
instructions[0xBF] = Instruction{.name = "LAX", .cycles = 4, .execute = &CPU::LAX, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xA3] = Instruction{.name = "LAX", .cycles = 6, .execute = &CPU::LAX, .fetch = &CPU::IndirectX};
|
||||
instructions[0xB3] = Instruction{.name = "LAX", .cycles = 5, .execute = &CPU::LAX, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0xC7] = Instruction{.cycles = 5, .execute = &CPU::DCP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xD7] = Instruction{.cycles = 6, .execute = &CPU::DCP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xCF] = Instruction{.cycles = 6, .execute = &CPU::DCP, .fetch = &CPU::Absolute};
|
||||
instructions[0xDF] = Instruction{.cycles = 7, .execute = &CPU::DCP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xDB] = Instruction{.cycles = 7, .execute = &CPU::DCP, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xC3] = Instruction{.cycles = 8, .execute = &CPU::DCP, .fetch = &CPU::IndirectX};
|
||||
instructions[0xD3] = Instruction{.cycles = 8, .execute = &CPU::DCP, .fetch = &CPU::IndirectY};
|
||||
instructions[0xC7] = Instruction{.name = "DCP", .cycles = 5, .execute = &CPU::DCP, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xD7] = Instruction{.name = "DCP", .cycles = 6, .execute = &CPU::DCP, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xCF] = Instruction{.name = "DCP", .cycles = 6, .execute = &CPU::DCP, .fetch = &CPU::Absolute};
|
||||
instructions[0xDF] = Instruction{.name = "DCP", .cycles = 7, .execute = &CPU::DCP, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xDB] = Instruction{.name = "DCP", .cycles = 7, .execute = &CPU::DCP, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xC3] = Instruction{.name = "DCP", .cycles = 8, .execute = &CPU::DCP, .fetch = &CPU::IndirectX};
|
||||
instructions[0xD3] = Instruction{.name = "DCP", .cycles = 8, .execute = &CPU::DCP, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0xE7] = Instruction{.cycles = 5, .execute = &CPU::ISC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xF7] = Instruction{.cycles = 6, .execute = &CPU::ISC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xEF] = Instruction{.cycles = 6, .execute = &CPU::ISC, .fetch = &CPU::Absolute};
|
||||
instructions[0xFF] = Instruction{.cycles = 7, .execute = &CPU::ISC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xFB] = Instruction{.cycles = 7, .execute = &CPU::ISC, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xE3] = Instruction{.cycles = 8, .execute = &CPU::ISC, .fetch = &CPU::IndirectX};
|
||||
instructions[0xF3] = Instruction{.cycles = 8, .execute = &CPU::ISC, .fetch = &CPU::IndirectY};
|
||||
instructions[0xE7] = Instruction{.name = "ISC", .cycles = 5, .execute = &CPU::ISC, .fetch = &CPU::ZeroPage};
|
||||
instructions[0xF7] = Instruction{.name = "ISC", .cycles = 6, .execute = &CPU::ISC, .fetch = &CPU::ZeroPageX};
|
||||
instructions[0xEF] = Instruction{.name = "ISC", .cycles = 6, .execute = &CPU::ISC, .fetch = &CPU::Absolute};
|
||||
instructions[0xFF] = Instruction{.name = "ISC", .cycles = 7, .execute = &CPU::ISC, .fetch = &CPU::AbsoluteX};
|
||||
instructions[0xFB] = Instruction{.name = "ISC", .cycles = 7, .execute = &CPU::ISC, .fetch = &CPU::AbsoluteY};
|
||||
instructions[0xE3] = Instruction{.name = "ISC", .cycles = 8, .execute = &CPU::ISC, .fetch = &CPU::IndirectX};
|
||||
instructions[0xF3] = Instruction{.name = "ISC", .cycles = 8, .execute = &CPU::ISC, .fetch = &CPU::IndirectY};
|
||||
|
||||
instructions[0x0B] = Instruction{.cycles = 2, .execute = &CPU::ANC, .fetch = &CPU::Immediate};
|
||||
instructions[0x2B] = Instruction{.cycles = 2, .execute = &CPU::ANC, .fetch = &CPU::Immediate};
|
||||
instructions[0x4B] = Instruction{.cycles = 0, .execute = &CPU::ALR, .fetch = &CPU::Immediate};
|
||||
instructions[0x6B] = Instruction{.cycles = 0, .execute = &CPU::ARR, .fetch = &CPU::Immediate};
|
||||
instructions[0xCB] = Instruction{.cycles = 0, .execute = &CPU::AXS, .fetch = &CPU::Immediate};
|
||||
instructions[0x0B] = Instruction{.name = "ANC", .cycles = 2, .execute = &CPU::ANC, .fetch = &CPU::Immediate};
|
||||
instructions[0x2B] = Instruction{.name = "ANC", .cycles = 2, .execute = &CPU::ANC, .fetch = &CPU::Immediate};
|
||||
instructions[0x4B] = Instruction{.name = "ALR", .cycles = 0, .execute = &CPU::ALR, .fetch = &CPU::Immediate};
|
||||
instructions[0x6B] = Instruction{.name = "ARR", .cycles = 0, .execute = &CPU::ARR, .fetch = &CPU::Immediate};
|
||||
instructions[0xCB] = Instruction{.name = "AXS", .cycles = 0, .execute = &CPU::AXS, .fetch = &CPU::Immediate};
|
||||
|
||||
// Unused by NES
|
||||
instructions[0x9C] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x9E] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x8B] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x93] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x9B] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x9F] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xBB] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x02] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x12] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x22] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x32] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x42] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x52] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x62] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x72] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x92] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xB2] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xD2] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xF2] = Instruction{.cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x9C] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x9E] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x8B] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x93] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x9B] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x9F] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xBB] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x02] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x12] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x22] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x32] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x42] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x52] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x62] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x72] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0x92] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xB2] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xD2] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
instructions[0xF2] = Instruction{.name = "ILL", .cycles = 0, .execute = &CPU::NOP, .fetch = &CPU::Implicit};
|
||||
}
|
||||
|
||||
void CPU::Reset()
|
||||
{
|
||||
uint8_t startAddressLsb = ReadMemory(RESET_VECTOR_LSB);
|
||||
uint8_t startAddressMsb = ReadMemory(RESET_VECTOR_MSB);
|
||||
uint16_t startAddress = ComposeAddress(startAddressMsb, startAddressLsb);
|
||||
|
||||
pc = startAddress;
|
||||
cycles = 7u;
|
||||
status.SetByte(0x34u);
|
||||
sp = 0xFDu;
|
||||
memset(ram, 0, RAM_SIZE);
|
||||
}
|
||||
|
||||
void CPU::StackPush(uint8_t val)
|
||||
|
|
@ -329,166 +348,21 @@ uint8_t CPU::StackPop()
|
|||
return ReadMemory(address);
|
||||
}
|
||||
|
||||
void CPU::WriteMemory(uint16_t address, uint8_t value)
|
||||
{
|
||||
// First five bits of address determines its mapping
|
||||
switch ((address & 0xF800u) >> 11u)
|
||||
{
|
||||
// RAM and mirrors
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
case 0x02:
|
||||
case 0x03:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x7FFu;
|
||||
|
||||
ram[translatedAddress] = value;
|
||||
break;
|
||||
}
|
||||
|
||||
// SRAM and mirrors
|
||||
case 0x0C:
|
||||
case 0x0D:
|
||||
case 0x0E:
|
||||
case 0x0F:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x1FFFu;
|
||||
|
||||
sram[translatedAddress] = value;
|
||||
break;
|
||||
}
|
||||
|
||||
// ROM (Low) and mirrors
|
||||
case 0x10:
|
||||
case 0x11:
|
||||
case 0x12:
|
||||
case 0x13:
|
||||
case 0x14:
|
||||
case 0x15:
|
||||
case 0x16:
|
||||
case 0x17:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x3FFFu;
|
||||
|
||||
romLow[translatedAddress] = value;
|
||||
break;
|
||||
}
|
||||
|
||||
// ROM (High) and mirrors
|
||||
case 0x18:
|
||||
case 0x19:
|
||||
case 0x1A:
|
||||
case 0x1B:
|
||||
case 0x1C:
|
||||
case 0x1D:
|
||||
case 0x1E:
|
||||
case 0x1F:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x3FFFu;
|
||||
|
||||
romHigh[translatedAddress] = value;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t CPU::ReadMemory(uint16_t address)
|
||||
{
|
||||
uint8_t byte{};
|
||||
|
||||
switch ((address & 0xF800u) >> 11u)
|
||||
{
|
||||
// RAM and mirrors
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
case 0x02:
|
||||
case 0x03:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x7FFu;
|
||||
|
||||
byte = ram[translatedAddress];
|
||||
break;
|
||||
}
|
||||
|
||||
// SRAM and mirrors
|
||||
case 0x0C:
|
||||
case 0x0D:
|
||||
case 0x0E:
|
||||
case 0x0F:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x1FFFu;
|
||||
|
||||
byte = sram[translatedAddress];
|
||||
break;
|
||||
}
|
||||
|
||||
// ROM (Low) and mirrors
|
||||
case 0x10:
|
||||
case 0x11:
|
||||
case 0x12:
|
||||
case 0x13:
|
||||
case 0x14:
|
||||
case 0x15:
|
||||
case 0x16:
|
||||
case 0x17:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x3FFFu;
|
||||
|
||||
byte = romLow[translatedAddress];
|
||||
break;
|
||||
}
|
||||
|
||||
// ROM (High) and mirrors
|
||||
case 0x18:
|
||||
case 0x19:
|
||||
case 0x1A:
|
||||
case 0x1B:
|
||||
case 0x1C:
|
||||
case 0x1D:
|
||||
case 0x1E:
|
||||
case 0x1F:
|
||||
{
|
||||
uint16_t translatedAddress = address & 0x3FFFu;
|
||||
|
||||
byte = romHigh[translatedAddress];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
void CPU::LoadRom(const char* filename)
|
||||