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2023-fpga-computer/src/sap1/top.v

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module top(
input CLK
);
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reg[7:0] bus;
always @(*) begin
if (ir_en) begin
bus = ir_out;
end else if (adder_en) begin
bus = adder_out;
end else if (a_en) begin
bus = a_out;
end else if (mem_en) begin
bus = mem_out;
end else if (pc_en) begin
bus = pc_out;
end else begin
bus = 8'b0;
end
end
wire rst;
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wire hlt;
wire clk;
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clock clock(
.hlt(hlt),
.clk_in(CLK),
.clk_out(clk)
);
wire pc_inc;
wire pc_en;
wire[7:0] pc_out;
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pc pc(
.clk(clk),
.rst(rst),
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.inc(pc_inc),
.out(pc_out)
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);
wire mar_load;
wire mem_en;
wire[7:0] mem_out;
memory mem(
.clk(clk),
.rst(rst),
.load(mar_load),
.bus(bus),
.out(mem_out)
);
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wire a_load;
wire a_en;
wire[7:0] a_out;
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reg_a reg_a(
.clk(clk),
.rst(rst),
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.load(a_load),
.bus(bus),
.out(a_out)
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);
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wire b_load;
wire[7:0] b_out;
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reg_b reg_b(
.clk(clk),
.rst(rst),
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.load(b_load),
.bus(bus),
.out(b_out)
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);
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wire adder_sub;
wire adder_en;
wire[7:0] adder_out;
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adder adder(
.a(a_out),
.b(b_out),
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.sub(adder_sub),
.out(adder_out)
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);
wire ir_load;
wire ir_en;
wire[7:0] ir_out;
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ir ir(
.clk(clk),
.rst(rst),
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.load(ir_load),
.bus(bus),
.out(ir_out)
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);
controller controller(
.clk(clk),
.rst(rst),
.opcode(ir_out[7:4]),
.out(
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{
hlt,
pc_inc,
pc_en,
mar_load,
mem_en,
ir_load,
ir_en,
a_load,
a_en,
b_load,
adder_sub,
adder_en
})
);
endmodule