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2023-fpga-computer/src/adder.v

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2023-01-04 02:26:45 +00:00
module adder(
input[7:0] a,
input[7:0] b,
input sub,
input en,
output[7:0] bus);
assign bus =
(en) ?
((sub) ? a-b : a+b) :
8'bz;
endmodule