21 lines
245 B
Coq
21 lines
245 B
Coq
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module reg_a(
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input clk,
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input load,
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input en,
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inout[7:0] bus,
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output[7:0] val);
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reg[7:0] reg_a = 0;
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always @(posedge clk) begin
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if (load) begin
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reg_a <= bus;
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end
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end
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assign bus = (en) ? reg_a : 8'bz;
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assign val = reg_a;
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endmodule
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