24 lines
310 B
Coq
24 lines
310 B
Coq
|
module ir(
|
||
|
input clk,
|
||
|
input clr,
|
||
|
input load,
|
||
|
input en,
|
||
|
inout[7:0] bus,
|
||
|
output[3:0] instr);
|
||
|
|
||
|
reg[7:0] ir = 0;
|
||
|
|
||
|
always @(posedge clk or posedge clr) begin
|
||
|
if (clr) begin
|
||
|
ir <= 8'b0;
|
||
|
end else if (load) begin
|
||
|
ir <= bus;
|
||
|
end
|
||
|
end
|
||
|
|
||
|
assign instr = ir[7:4];
|
||
|
assign bus = (en) ? ir[3:0] : 8'bz;
|
||
|
|
||
|
endmodule
|
||
|
|