24 lines
310 B
Verilog
24 lines
310 B
Verilog
module ir(
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input clk,
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input clr,
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input load,
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input en,
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inout[7:0] bus,
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output[3:0] instr);
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reg[7:0] ir = 0;
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always @(posedge clk or posedge clr) begin
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if (clr) begin
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ir <= 8'b0;
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end else if (load) begin
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ir <= bus;
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end
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end
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assign instr = ir[7:4];
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assign bus = (en) ? ir[3:0] : 8'bz;
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endmodule
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