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Add rst and remove en from SAP-1 and SAP-2

This commit is contained in:
Austin Morlan 2023-02-16 19:25:05 -08:00
parent 03d0d5c982
commit eb7cc9dc79
Signed by: austin
GPG Key ID: FD6B27654AF5E348
19 changed files with 448 additions and 449 deletions

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@ -2,13 +2,10 @@ module adder(
input[7:0] a, input[7:0] a,
input[7:0] b, input[7:0] b,
input sub, input sub,
input en, output[7:0] out
output[7:0] bus); );
assign bus = assign out = (sub) ? a-b : a+b;
(en) ?
((sub) ? a-b : a+b) :
8'bz;
endmodule endmodule

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@ -1,7 +1,8 @@
module clock( module clock(
input hlt, input hlt,
input clk_in, input clk_in,
output clk_out); output clk_out
);
assign clk_out = (hlt) ? 1'b0 : clk_in; assign clk_out = (hlt) ? 1'b0 : clk_in;

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@ -1,7 +1,9 @@
module controller( module controller(
input clk, input clk,
input[3:0] instr, input rst,
output reg[11:0] ctrl_word); input[3:0] opcode,
output[11:0] out
);
localparam SIG_HLT = 11; localparam SIG_HLT = 11;
localparam SIG_PC_INC = 10; localparam SIG_PC_INC = 10;
@ -21,103 +23,88 @@ localparam OP_ADD = 4'b0001;
localparam OP_SUB = 4'b0010; localparam OP_SUB = 4'b0010;
localparam OP_HLT = 4'b1111; localparam OP_HLT = 4'b1111;
reg[2:0] stage = 0; reg[2:0] stage;
reg[11:0] ctrl_word;
always @(negedge clk) begin always @(negedge clk, posedge rst) begin
if (stage == 6) begin if (rst) begin
stage <= 1; stage <= 0;
end else begin
if (stage == 5) begin
stage <= 0;
end else begin end else begin
stage <= stage + 1; stage <= stage + 1;
end end
end end
end
always @(*) begin always @(*) begin
case (stage)
1: begin
ctrl_word = 12'b0; ctrl_word = 12'b0;
case (stage)
0: begin
ctrl_word[SIG_PC_EN] = 1; ctrl_word[SIG_PC_EN] = 1;
ctrl_word[SIG_MEM_LOAD] = 1; ctrl_word[SIG_MEM_LOAD] = 1;
end end
2: begin 1: begin
ctrl_word = 12'b0;
ctrl_word[SIG_PC_INC] = 1; ctrl_word[SIG_PC_INC] = 1;
end end
3: begin 2: begin
ctrl_word = 12'b0;
ctrl_word[SIG_MEM_EN] = 1; ctrl_word[SIG_MEM_EN] = 1;
ctrl_word[SIG_IR_LOAD] = 1; ctrl_word[SIG_IR_LOAD] = 1;
end end
4: begin 3: begin
case (instr) case (opcode)
OP_LDA: begin OP_LDA: begin
ctrl_word = 12'b0;
ctrl_word[SIG_IR_EN] = 1; ctrl_word[SIG_IR_EN] = 1;
ctrl_word[SIG_MEM_LOAD] = 1; ctrl_word[SIG_MEM_LOAD] = 1;
end end
OP_ADD: begin OP_ADD: begin
ctrl_word = 12'b0;
ctrl_word[SIG_IR_EN] = 1; ctrl_word[SIG_IR_EN] = 1;
ctrl_word[SIG_MEM_LOAD] = 1; ctrl_word[SIG_MEM_LOAD] = 1;
end end
OP_SUB: begin OP_SUB: begin
ctrl_word = 12'b0;
ctrl_word[SIG_IR_EN] = 1; ctrl_word[SIG_IR_EN] = 1;
ctrl_word[SIG_MEM_LOAD] = 1; ctrl_word[SIG_MEM_LOAD] = 1;
end end
OP_HLT: begin OP_HLT: begin
ctrl_word = 12'b0;
ctrl_word[SIG_HLT] = 1; ctrl_word[SIG_HLT] = 1;
end end
default: begin endcase
ctrl_word = 12'b0; end
4: begin
case (opcode)
OP_LDA: begin
ctrl_word[SIG_MEM_EN] = 1;
ctrl_word[SIG_A_LOAD] = 1;
end
OP_ADD: begin
ctrl_word[SIG_MEM_EN] = 1;
ctrl_word[SIG_B_LOAD] = 1;
end
OP_SUB: begin
ctrl_word[SIG_MEM_EN] = 1;
ctrl_word[SIG_B_LOAD] = 1;
end end
endcase endcase
end end
5: begin 5: begin
case (instr) case (opcode)
OP_LDA: begin
ctrl_word = 12'b0;
ctrl_word[SIG_MEM_EN] = 1;
ctrl_word[SIG_A_LOAD] = 1;
end
OP_ADD: begin OP_ADD: begin
ctrl_word = 12'b0;
ctrl_word[SIG_MEM_EN] = 1;
ctrl_word[SIG_B_LOAD] = 1;
end
OP_SUB: begin
ctrl_word = 12'b0;
ctrl_word[SIG_MEM_EN] = 1;
ctrl_word[SIG_B_LOAD] = 1;
end
default: begin
ctrl_word = 12'b0;
end
endcase
end
6: begin
case (instr)
OP_ADD: begin
ctrl_word = 12'b0;
ctrl_word[SIG_ADDER_EN] = 1; ctrl_word[SIG_ADDER_EN] = 1;
ctrl_word[SIG_A_LOAD] = 1; ctrl_word[SIG_A_LOAD] = 1;
end end
OP_SUB: begin OP_SUB: begin
ctrl_word = 12'b0;
ctrl_word[SIG_ADDER_SUB] = 1; ctrl_word[SIG_ADDER_SUB] = 1;
ctrl_word[SIG_ADDER_EN] = 1; ctrl_word[SIG_ADDER_EN] = 1;
ctrl_word[SIG_A_LOAD] = 1; ctrl_word[SIG_A_LOAD] = 1;
end end
default: begin endcase
ctrl_word = 12'b0;
end
endcase
end
default: begin
ctrl_word = 12'b0;
end end
endcase endcase
end end
assign out = ctrl_word;
endmodule endmodule

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@ -1,23 +1,22 @@
module ir( module ir(
input clk, input clk,
input clr, input rst,
input load, input load,
input en, input[7:0] bus,
inout[7:0] bus, output[7:0] out
output[3:0] instr); );
reg[7:0] ir = 0; reg[7:0] ir;
always @(posedge clk or posedge clr) begin always @(posedge clk, posedge rst) begin
if (clr) begin if (rst) begin
ir <= 8'b0; ir <= 8'b0;
end else if (load) begin end else if (load) begin
ir <= bus; ir <= bus;
end end
end end
assign instr = ir[7:4]; assign out = ir;
assign bus = (en) ? ir[3:0] : 8'bz;
endmodule endmodule

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@ -1,24 +1,27 @@
module memory( module memory(
input clk, input clk,
input rst,
input load, input load,
input en, input[7:0] bus,
inout[7:0] bus output[7:0] out
); );
initial begin initial begin
$readmemh("program.bin", ram); $readmemh("program.bin", ram);
end end
reg[3:0] mar = 0; reg[3:0] mar;
reg[7:0] ram[0:15]; reg[7:0] ram[0:15];
always @(posedge clk) begin always @(posedge clk, posedge rst) begin
if (load) begin if (rst) begin
mar <= 4'b0;
end else if (load) begin
mar <= bus[3:0]; mar <= bus[3:0];
end end
end end
assign bus = (en) ? ram[mar] : 8'bz; assign out = ram[mar];
endmodule endmodule

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@ -1,22 +1,21 @@
module pc( module pc(
input clk, input clk,
input clr, input rst,
input inc, input inc,
input en, output[7:0] out
output[7:0] bus
); );
reg[3:0] pc = 0; reg[3:0] pc;
always @(posedge clk or posedge clr) begin always @(posedge clk, posedge rst) begin
if (clr) begin if (rst) begin
pc <= 4'b0; pc <= 4'b0;
end else if (inc) begin end else if (inc) begin
pc <= pc + 1; pc <= pc + 1;
end end
end end
assign bus = (en) ? pc : 8'bz; assign out = pc;
endmodule endmodule

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@ -1,20 +1,22 @@
module reg_a( module reg_a(
input clk, input clk,
input rst,
input load, input load,
input en, input[7:0] bus,
inout[7:0] bus, output[7:0] out
output[7:0] val); );
reg[7:0] reg_a = 0; reg[7:0] reg_a;
always @(posedge clk) begin always @(posedge clk, posedge rst) begin
if (load) begin if (rst) begin
reg_a <= 8'b0;
end else if (load) begin
reg_a <= bus; reg_a <= bus;
end end
end end
assign bus = (en) ? reg_a : 8'bz; assign out = reg_a;
assign val = reg_a;
endmodule endmodule

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@ -1,18 +1,22 @@
module reg_b( module reg_b(
input clk, input clk,
input rst,
input load, input load,
input[7:0] bus, input[7:0] bus,
output[7:0] val); output[7:0] out
);
reg[7:0] reg_b = 0; reg[7:0] reg_b;
always @(posedge clk) begin always @(posedge clk, posedge rst) begin
if (load) begin if (rst) begin
reg_b <= 8'b0;
end else if (load) begin
reg_b <= bus; reg_b <= bus;
end end
end end
assign val = reg_b; assign out = reg_b;
endmodule endmodule

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@ -1,82 +1,108 @@
module top( module top(
input CLK); input CLK
);
wire[7:0] bus;
wire clk; reg[7:0] bus;
always @(*) begin
if (ir_en) begin
bus = ir_out;
end else if (adder_en) begin
bus = adder_out;
end else if (a_en) begin
bus = a_out;
end else if (mem_en) begin
bus = mem_out;
end else if (pc_en) begin
bus = pc_out;
end else begin
bus = 8'b0;
end
end
wire rst;
wire hlt; wire hlt;
wire clk;
clock clock( clock clock(
.hlt(hlt), .hlt(hlt),
.clk_in(CLK), .clk_in(CLK),
.clk_out(clk) .clk_out(clk)
); );
wire clr;
wire pc_en;
wire pc_inc; wire pc_inc;
wire pc_en;
wire[7:0] pc_out;
pc pc( pc pc(
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.inc(pc_inc), .inc(pc_inc),
.en(pc_en), .out(pc_out)
.bus(bus)
); );
wire a_load;
wire a_en;
wire[7:0] a_val;
reg_a reg_a(
.clk(clk),
.load(a_load),
.en(a_en),
.bus(bus),
.val(a_val)
);
wire b_load;
wire[7:0] b_val;
reg_b reg_b(
.clk(clk),
.load(b_load),
.bus(bus),
.val(b_val)
);
wire adder_sub;
wire adder_en;
adder adder(
.a(a_val),
.b(b_val),
.sub(adder_sub),
.en(adder_en),
.bus(bus)
);
wire mar_load; wire mar_load;
wire mem_en; wire mem_en;
wire[7:0] mem_out;
memory mem( memory mem(
.clk(clk), .clk(clk),
.rst(rst),
.load(mar_load), .load(mar_load),
.en(mem_en), .bus(bus),
.bus(bus) .out(mem_out)
); );
wire a_load;
wire a_en;
wire[7:0] a_out;
reg_a reg_a(
.clk(clk),
.rst(rst),
.load(a_load),
.bus(bus),
.out(a_out)
);
wire b_load;
wire[7:0] b_out;
reg_b reg_b(
.clk(clk),
.rst(rst),
.load(b_load),
.bus(bus),
.out(b_out)
);
wire adder_sub;
wire adder_en;
wire[7:0] adder_out;
adder adder(
.a(a_out),
.b(b_out),
.sub(adder_sub),
.out(adder_out)
);
wire ir_load; wire ir_load;
wire ir_en; wire ir_en;
wire[3:0] ir_instr; wire[7:0] ir_out;
ir ir( ir ir(
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.load(ir_load), .load(ir_load),
.en(ir_en),
.bus(bus), .bus(bus),
.instr(ir_instr) .out(ir_out)
); );
controller controller( controller controller(
.clk(clk), .clk(clk),
.instr(ir_instr), .rst(rst),
.ctrl_word( .opcode(ir_out[7:4]),
.out(
{ {
hlt, hlt,
pc_inc, pc_inc,

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@ -1,8 +1,29 @@
module top_tb(); module top_tb();
initial begin initial begin
$dumpfile("top_tb.vcd"); $dumpfile("top_tb.vcd");
$dumpvars(0, top_tb); $dumpvars(0, top_tb);
rst = 1;
#1 rst = 0;
end
reg[7:0] bus;
always @(*) begin
if (ir_en) begin
bus = ir_out;
end else if (adder_en) begin
bus = adder_out;
end else if (a_en) begin
bus = a_out;
end else if (mem_en) begin
bus = mem_out;
end else if (pc_en) begin
bus = pc_out;
end else begin
bus = 8'b0;
end
end end
reg clk_in = 0; reg clk_in = 0;
@ -15,80 +36,86 @@ end
wire clk; wire clk;
wire hlt; wire hlt;
wire clr; reg rst;
wire[7:0] bus;
clock clock( clock clock(
.hlt(hlt), .hlt(hlt),
.clk_in(clk_in), .clk_in(clk_in),
.clk_out(clk) .clk_out(clk)
); );
wire pc_en;
wire pc_inc; wire pc_inc;
wire[7:0] pc_out;
wire pc_en;
pc pc( pc pc(
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.inc(pc_inc), .inc(pc_inc),
.en(pc_en), .out(pc_out)
.bus(bus)
); );
wire a_load;
wire a_en;
wire[7:0] a_val;
reg_a reg_a(
.clk(clk),
.load(a_load),
.en(a_en),
.bus(bus),
.val(a_val)
);
wire b_load;
wire[7:0] b_val;
reg_b reg_b(
.clk(clk),
.load(b_load),
.bus(bus),
.val(b_val)
);
wire adder_sub;
wire adder_en;
adder adder(
.a(a_val),
.b(b_val),
.sub(adder_sub),
.en(adder_en),
.bus(bus)
);
wire mar_load; wire mar_load;
wire mem_en; wire mem_en;
wire[7:0] mem_out;
memory mem( memory mem(
.clk(clk), .clk(clk),
.rst(rst),
.load(mar_load), .load(mar_load),
.en(mem_en), .bus(bus),
.bus(bus) .out(mem_out)
); );
wire a_load;
wire a_en;
wire[7:0] a_out;
reg_a reg_a(
.clk(clk),
.rst(rst),
.load(a_load),
.bus(bus),
.out(a_out)
);
wire b_load;
wire[7:0] b_out;
reg_b reg_b(
.clk(clk),
.rst(rst),
.load(b_load),
.bus(bus),
.out(b_out)
);
wire adder_sub;
wire adder_en;
wire[7:0] adder_out;
adder adder(
.a(a_out),
.b(b_out),
.sub(adder_sub),
.out(adder_out)
);
wire ir_load; wire ir_load;
wire ir_en; wire ir_en;
wire[3:0] ir_instr; wire[7:0] ir_out;
ir ir( ir ir(
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.load(ir_load), .load(ir_load),
.en(ir_en),
.bus(bus), .bus(bus),
.instr(ir_instr) .out(ir_out)
); );
controller controller( controller controller(
.clk(clk), .clk(clk),
.instr(ir_instr), .rst(rst),
.ctrl_word( .opcode(ir_out[7:4]),
.out(
{ {
hlt, hlt,
pc_inc, pc_inc,

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@ -1,14 +1,15 @@
module alu( module alu(
input clk, input clk,
input rst,
input[7:0] a, input[7:0] a,
input[2:0] op, input[2:0] op,
input load, input load,
input en, input[15:0] bus,
inout[15:0] bus output[7:0] out
); );
reg[7:0] alu = 0; reg[7:0] alu;
reg[7:0] tmp = 0; reg[7:0] tmp;
localparam OP_ADD = 0; localparam OP_ADD = 0;
localparam OP_SUB = 1; localparam OP_SUB = 1;
@ -19,8 +20,10 @@ localparam OP_CMA = 5;
localparam OP_RAL = 6; localparam OP_RAL = 6;
localparam OP_RAR = 7; localparam OP_RAR = 7;
always @(posedge clk) begin always @(posedge clk, posedge rst) begin
if (load) begin if (rst) begin
tmp <= 8'b0;
end else if (load) begin
tmp <= bus[7:0]; tmp <= bus[7:0];
end end
end end
@ -58,7 +61,7 @@ always @(*) begin
endcase endcase
end end
assign bus = (en) ? alu : 16'bz; assign out = alu;
endmodule endmodule

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@ -1,8 +1,9 @@
module controller( module controller(
input clk, input clk,
input[7:0] instr, input rst,
input[7:0] opcode,
input[1:0] flags, input[1:0] flags,
output reg[33:0] ctrl_word output[33:0] out
); );
localparam SIG_END = 34; localparam SIG_END = 34;
@ -48,33 +49,41 @@ localparam OP_JM = 8'hFA;
localparam FLAG_Z = 1; localparam FLAG_Z = 1;
localparam FLAG_S = 0; localparam FLAG_S = 0;
reg[34:0] ctrl_word;
reg[34:0] ctrl_rom[0:4095]; reg[34:0] ctrl_rom[0:4095];
initial begin initial begin
$readmemb("ctrl_rom.bin", ctrl_rom); $readmemb("ctrl_rom.bin", ctrl_rom);
end end
reg reset = 0; reg[3:0] stage;
reg[3:0] stage = 0; always @(negedge clk, posedge rst) begin
always @(negedge clk) begin if (rst) begin
if (reset) begin stage <= 0;
end else begin
if (stage_rst) begin
stage <= 0; stage <= 0;
end else begin end else begin
stage <= stage + 1; stage <= stage + 1;
end end
end end
end
reg stage_rst;
always @(*) begin always @(*) begin
ctrl_word = ctrl_rom[{instr, stage}]; ctrl_word = ctrl_rom[{opcode, stage}];
if ((instr == OP_JZ && stage == 4 && flags[FLAG_Z] == 0) || if ((opcode == OP_JZ && stage == 4 && flags[FLAG_Z] == 0) ||
(instr == OP_JNZ && stage == 4 && flags[FLAG_Z] == 1) || (opcode == OP_JNZ && stage == 4 && flags[FLAG_Z] == 1) ||
(instr == OP_JM && stage == 4 && flags[FLAG_S] == 0)) (opcode == OP_JM && stage == 4 && flags[FLAG_S] == 0))
begin begin
reset = 1; stage_rst = 1;
end else begin end else begin
reset = ctrl_rom[{instr, stage}][SIG_END]; stage_rst = ctrl_rom[{opcode, stage}][SIG_END];
end end
end end
assign out = ctrl_word;
endmodule endmodule

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@ -1,5 +1,6 @@
module flags( module flags(
input clk, input clk,
input rst,
input[7:0] a, input[7:0] a,
input[7:0] b, input[7:0] b,
input[7:0] c, input[7:0] c,
@ -12,22 +13,24 @@ module flags(
localparam FLAG_Z = 1; localparam FLAG_Z = 1;
localparam FLAG_S = 0; localparam FLAG_S = 0;
reg[1:0] data = 0; reg[1:0] flags;
always @(negedge clk) begin always @(negedge clk, posedge rst) begin
if (load_a) begin if (rst) begin
data[FLAG_Z] <= (a == 0) ? 1'b1 : 1'b0; flags <= 2'b0;
data[FLAG_S] <= (a[7] == 1) ? 1'b1 : 1'b0; end else if (load_a) begin
flags[FLAG_Z] <= (a == 0) ? 1'b1 : 1'b0;
flags[FLAG_S] <= (a[7] == 1) ? 1'b1 : 1'b0;
end else if (load_b) begin end else if (load_b) begin
data[FLAG_Z] <= (b == 0) ? 1'b1 : 1'b0; flags[FLAG_Z] <= (b == 0) ? 1'b1 : 1'b0;
data[FLAG_S] <= (b[7] == 1) ? 1'b1 : 1'b0; flags[FLAG_S] <= (b[7] == 1) ? 1'b1 : 1'b0;
end else if (load_c) begin end else if (load_c) begin
data[FLAG_Z] <= (c == 0) ? 1'b1 : 1'b0; flags[FLAG_Z] <= (c == 0) ? 1'b1 : 1'b0;
data[FLAG_S] <= (c[7] == 1) ? 1'b1 : 1'b0; flags[FLAG_S] <= (c[7] == 1) ? 1'b1 : 1'b0;
end end
end end
assign out = data; assign out = flags;
endmodule endmodule

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@ -1,22 +1,22 @@
module ir( module ir(
input clk, input clk,
input clr, input rst,
input load, input load,
input[15:0] bus, input[15:0] bus,
output[7:0] out output[7:0] out
); );
reg[7:0] data = 0; reg[7:0] ir;
always @(posedge clk or posedge clr) begin always @(posedge clk, posedge rst) begin
if (clr) begin if (rst) begin
data <= 8'b0; ir <= 8'b0;
end else if (load) begin end else if (load) begin
data <= bus[7:0]; ir <= bus[7:0];
end end
end end
assign out = data; assign out = ir;
endmodule endmodule

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@ -1,25 +1,31 @@
module memory( module memory(
input clk, input clk,
input rst,
input mar_loadh, input mar_loadh,
input mar_loadl, input mar_loadl,
input mdr_load, input mdr_load,
input mdr_en,
input ram_load, input ram_load,
input ram_enh, input ram_enh,
input ram_enl, input ram_enl,
input call, input call,
input ret, input ret,
inout[15:0] bus input[15:0] bus,
output[15:0] out
); );
initial begin initial begin
$readmemh("program.bin", ram); $readmemh("program.bin", ram);
end end
reg[15:0] mar = 0; reg[15:0] mar;
reg[15:0] mdr = 0; reg[15:0] mdr;
reg[7:0] ram[0:65535]; reg[7:0] ram[0:65535];
always @(posedge rst) begin
mar <= 16'b0;
mdr <= 16'b0;
end
always @(posedge clk) begin always @(posedge clk) begin
if (mar_loadh) begin if (mar_loadh) begin
mar[15:8] <= bus[15:8]; mar[15:8] <= bus[15:8];
@ -33,30 +39,22 @@ always @(posedge clk) begin
mdr[7:0] <= bus[7:0]; mdr[7:0] <= bus[7:0];
end end
if (ram_load) begin
ram[mar] <= mdr;
end
if (ram_enh) begin
mdr[15:8] <= ram[mar];
end
if (ram_enl) begin
mdr[7:0] <= ram[mar];
end
if (call) begin
ram[16'hFFFE] <= bus[15:8];
ram[16'hFFFF] <= bus[7:0];
end
if (ret) begin if (ret) begin
mdr[15:8] <= ram[16'hFFFE]; mdr[15:8] <= ram[16'hFFFE];
mdr[7:0] <= ram[16'hFFFF]; mdr[7:0] <= ram[16'hFFFF];
end else if (call) begin
ram[16'hFFFE] <= bus[15:8];
ram[16'hFFFF] <= bus[7:0];
end else if (ram_enh) begin
mdr[15:8] <= ram[mar];
end else if (ram_enl) begin
mdr[7:0] <= ram[mar];
end else if (ram_load) begin
ram[mar] <= mdr;
end end
end end
assign bus = (mdr_en) ? mdr : 16'bz; assign out = mdr;
endmodule endmodule

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@ -1,16 +1,16 @@
module pc( module pc(
input clk, input clk,
input clr, input rst,
input inc, input inc,
input load, input load,
input en, input[15:0] bus,
output[15:0] bus output[15:0] out
); );
reg[15:0] pc = 0; reg[15:0] pc;
always @(posedge clk or posedge clr) begin always @(posedge clk, posedge rst) begin
if (clr) begin if (rst) begin
pc <= 16'b0; pc <= 16'b0;
end else if (load) begin end else if (load) begin
pc <= bus; pc <= bus;
@ -19,7 +19,7 @@ always @(posedge clk or posedge clr) begin
end end
end end
assign bus = (en) ? pc : 16'bz; assign out = pc;
endmodule endmodule

View File

@ -1,17 +1,19 @@
module register( module register(
input clk, input clk,
input rst,
input load, input load,
input en,
input inc, input inc,
input dec, input dec,
inout[15:0] bus, input[15:0] bus,
output[7:0] out output[7:0] out
); );
reg[7:0] data = 0; reg[7:0] data;
always @(posedge clk) begin always @(posedge clk, posedge rst) begin
if (load) begin if (rst) begin
data <= 8'b0;
end else if (load) begin
data <= bus[7:0]; data <= bus[7:0];
end else if (inc) begin end else if (inc) begin
data <= data + 1; data <= data + 1;
@ -20,7 +22,6 @@ always @(posedge clk) begin
end end
end end
assign bus = (en) ? {8'b0, data} : 16'bz;
assign out = data; assign out = data;
endmodule endmodule

View File

@ -3,49 +3,57 @@ module top(
); );
wire[15:0] bus; reg[15:0] bus;
wire clr;
always @(*) begin
if (a_en) begin
bus = a_out;
end else if (b_en) begin
bus = b_out;
end else if (c_en) begin
bus = c_out;
end else if (alu_en) begin
bus = alu_out;
end else if (pc_en) begin
bus = pc_out;
end else if (mdr_en) begin
bus = mem_out;
end else begin
bus = 16'b0;
end
end
wire rst;
wire hlt; wire hlt;
wire clk; wire clk;
clock clock( clock clock(
// In
.hlt(hlt), .hlt(hlt),
.clk_in(CLK), .clk_in(CLK),
// Out
.clk_out(clk) .clk_out(clk)
); );
wire pc_inc; wire pc_inc;
wire pc_load; wire pc_load;
wire pc_en; wire pc_en;
wire[15:0] pc_out;
pc pc( pc pc(
// In
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.inc(pc_inc), .inc(pc_inc),
.load(pc_load), .load(pc_load),
.en(pc_en), .bus(bus),
.out(pc_out)
// Output
.bus(bus)
); );
wire ir_load; wire ir_load;
wire[7:0] ir_instr; wire[7:0] ir_out;
ir ir( ir ir(
// In
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.load(ir_load), .load(ir_load),
// Inout
.bus(bus), .bus(bus),
.out(ir_out)
// Out
.out(ir_instr)
); );
wire mar_loadh; wire mar_loadh;
@ -57,153 +65,115 @@ wire ram_enh;
wire ram_enl; wire ram_enl;
wire call; wire call;
wire ret; wire ret;
wire[15:0] mem_out;
memory mem( memory mem(
// In
.clk(clk), .clk(clk),
.rst(rst),
.mar_loadh(mar_loadh), .mar_loadh(mar_loadh),
.mar_loadl(mar_loadl), .mar_loadl(mar_loadl),
.mdr_load(mdr_load), .mdr_load(mdr_load),
.mdr_en(mdr_en),
.ram_load(ram_load), .ram_load(ram_load),
.ram_enh(ram_enh), .ram_enh(ram_enh),
.ram_enl(ram_enl), .ram_enl(ram_enl),
.call(call), .call(call),
.ret(ret), .ret(ret),
.bus(bus),
// Inout .out(mem_out)
.bus(bus)
); );
wire a_load; wire a_load;
wire a_en; wire a_en;
wire a_inc; wire a_inc;
wire a_dec; wire a_dec;
wire[7:0] a_val; wire[7:0] a_out;
register reg_a( register reg_a(
// In
.clk(clk), .clk(clk),
.rst(rst),
.load(a_load), .load(a_load),
.en(a_en),
.inc(a_inc), .inc(a_inc),
.dec(a_dec), .dec(a_dec),
// Inout
.bus(bus), .bus(bus),
.out(a_out)
// Out
.out(a_val)
); );
wire b_load; wire b_load;
wire b_en; wire b_en;
wire b_inc; wire b_inc;
wire b_dec; wire b_dec;
wire[7:0] b_val; wire[7:0] b_out;
register reg_b( register reg_b(
// In
.clk(clk), .clk(clk),
.rst(rst),
.load(b_load), .load(b_load),
.en(b_en),
.inc(b_inc), .inc(b_inc),
.dec(b_dec), .dec(b_dec),
// Inout
.bus(bus), .bus(bus),
.out(b_out)
// Out
.out(b_val)
); );
wire c_load; wire c_load;
wire c_en; wire c_en;
wire c_inc; wire c_inc;
wire c_dec; wire c_dec;
wire[7:0] c_val; wire[7:0] c_out;
register reg_c( register reg_c(
// In
.clk(clk), .clk(clk),
.rst(rst),
.load(c_load), .load(c_load),
.en(c_en),
.inc(c_inc), .inc(c_inc),
.dec(c_dec), .dec(c_dec),
// Inout
.bus(bus), .bus(bus),
.out(c_out)
// Out
.out(c_val)
); );
wire[2:0] alu_op; wire[2:0] alu_op;
wire alu_load; wire alu_load;
wire alu_en; wire alu_en;
wire[7:0] alu_out;
alu alu( alu alu(
// In
.clk(clk), .clk(clk),
.a(a_val), .rst(rst),
.a(a_out),
.load(alu_load), .load(alu_load),
.op(alu_op), .op(alu_op),
.en(alu_en), .bus(bus),
.out(alu_out)
// Out
.bus(bus)
); );
wire[1:0] flags_val; wire[1:0] flags_out;
wire flags_lda; wire flags_lda;
wire flags_ldb; wire flags_ldb;
wire flags_ldc; wire flags_ldc;
flags flags( flags flags(
// In
.clk(clk), .clk(clk),
.a(a_val), .rst(rst),
.b(b_val), .a(a_out),
.c(c_val), .b(b_out),
.c(c_out),
.load_a(flags_lda), .load_a(flags_lda),
.load_b(flags_ldb), .load_b(flags_ldb),
.load_c(flags_ldc), .load_c(flags_ldc),
.out(flags_out)
// Out
.out(flags_val)
); );
controller controller( controller controller(
.clk(clk), .clk(clk),
.instr(ir_instr), .rst(rst),
.flags(flags_val), .opcode(ir_out),
.ctrl_word({ .flags(flags_out),
.out({
hlt, hlt,
a_load, a_load, a_en, a_inc, a_dec,
a_en, b_load, b_en, b_inc, b_dec,
a_inc, c_load, c_en, c_inc, c_dec,
a_dec, flags_lda, flags_ldb, flags_ldc,
b_load, alu_op, alu_load, alu_en,
b_en,
b_inc,
b_dec,
c_load,
c_en,
c_inc,
c_dec,
flags_lda,
flags_ldb,
flags_ldc,
alu_op,
alu_load,
alu_en,
ir_load, ir_load,
pc_inc, pc_inc, pc_load, pc_en,
pc_load, mar_loadh, mar_loadl, mdr_load,
pc_en,
mar_loadh,
mar_loadl,
mdr_load,
mdr_en, mdr_en,
ram_load, ram_load, ram_enh, ram_enl,
ram_enh, call, ret})
ram_enl,
call,
ret})
); );
endmodule endmodule

View File

@ -4,8 +4,29 @@ module top_tb();
initial begin initial begin
$dumpfile("top_tb.vcd"); $dumpfile("top_tb.vcd");
$dumpvars(0, top_tb); $dumpvars(0, top_tb);
rst = 1;
#1 rst = 0;
end end
reg[15:0] bus;
always @(*) begin
if (a_en) begin
bus = a_out;
end else if (b_en) begin
bus = b_out;
end else if (c_en) begin
bus = c_out;
end else if (alu_en) begin
bus = alu_out;
end else if (pc_en) begin
bus = pc_out;
end else if (mdr_en) begin
bus = mem_out;
end else begin
bus = 16'b0;
end
end
reg clk_in = 0; reg clk_in = 0;
integer i; integer i;
@ -15,49 +36,36 @@ initial begin
end end
end end
reg rst;
wire hlt; wire hlt;
wire clr = 0;
wire[15:0] bus;
wire clk; wire clk;
clock clock( clock clock(
// In
.hlt(hlt), .hlt(hlt),
.clk_in(clk_in), .clk_in(clk_in),
// Out
.clk_out(clk) .clk_out(clk)
); );
wire pc_inc; wire pc_inc;
wire pc_load; wire pc_load;
wire pc_en; wire pc_en;
wire[15:0] pc_out;
pc pc( pc pc(
// In
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.inc(pc_inc), .inc(pc_inc),
.load(pc_load), .load(pc_load),
.en(pc_en), .bus(bus),
.out(pc_out)
// Output
.bus(bus)
); );
wire ir_load; wire ir_load;
wire[7:0] ir_val; wire[7:0] ir_out;
ir ir( ir ir(
// In
.clk(clk), .clk(clk),
.clr(clr), .rst(rst),
.load(ir_load), .load(ir_load),
// Inout
.bus(bus), .bus(bus),
.out(ir_out)
// Out
.out(ir_val)
); );
wire mar_loadh; wire mar_loadh;
@ -69,153 +77,115 @@ wire ram_enh;
wire ram_enl; wire ram_enl;
wire call; wire call;
wire ret; wire ret;
wire[15:0] mem_out;
memory mem( memory mem(
// In
.clk(clk), .clk(clk),
.rst(rst),
.mar_loadh(mar_loadh), .mar_loadh(mar_loadh),
.mar_loadl(mar_loadl), .mar_loadl(mar_loadl),
.mdr_load(mdr_load), .mdr_load(mdr_load),
.mdr_en(mdr_en),
.ram_load(ram_load), .ram_load(ram_load),
.ram_enh(ram_enh), .ram_enh(ram_enh),
.ram_enl(ram_enl), .ram_enl(ram_enl),
.call(call), .call(call),
.ret(ret), .ret(ret),
.bus(bus),
// Inout .out(mem_out)
.bus(bus)
); );
wire a_load; wire a_load;
wire a_en; wire a_en;
wire a_inc; wire a_inc;
wire a_dec; wire a_dec;
wire[7:0] a_val; wire[7:0] a_out;
register reg_a( register reg_a(
// In
.clk(clk), .clk(clk),
.rst(rst),
.load(a_load), .load(a_load),
.en(a_en),
.inc(a_inc), .inc(a_inc),
.dec(a_dec), .dec(a_dec),
// Inout
.bus(bus), .bus(bus),
.out(a_out)
// Out
.out(a_val)
); );
wire b_load; wire b_load;
wire b_en; wire b_en;
wire b_inc; wire b_inc;
wire b_dec; wire b_dec;
wire[7:0] b_val; wire[7:0] b_out;
register reg_b( register reg_b(
// In
.clk(clk), .clk(clk),
.rst(rst),
.load(b_load), .load(b_load),
.en(b_en),
.inc(b_inc), .inc(b_inc),
.dec(b_dec), .dec(b_dec),
// Inout
.bus(bus), .bus(bus),
.out(b_out)
// Out
.out(b_val)
); );
wire c_load; wire c_load;
wire c_en; wire c_en;
wire c_inc; wire c_inc;
wire c_dec; wire c_dec;
wire[7:0] c_val; wire[7:0] c_out;
register reg_c( register reg_c(
// In
.clk(clk), .clk(clk),
.rst(rst),
.load(c_load), .load(c_load),
.en(c_en),
.inc(c_inc), .inc(c_inc),
.dec(c_dec), .dec(c_dec),
// Inout
.bus(bus), .bus(bus),
.out(c_out)
// Out
.out(c_val)
); );
wire[2:0] alu_op; wire[2:0] alu_op;
wire alu_load; wire alu_load;
wire alu_en; wire alu_en;
wire[7:0] alu_out;
alu alu( alu alu(
// In
.clk(clk), .clk(clk),
.a(a_val), .rst(rst),
.a(a_out),
.load(alu_load), .load(alu_load),
.op(alu_op), .op(alu_op),
.en(alu_en), .bus(bus),
.out(alu_out)
// Inout
.bus(bus)
); );
wire[1:0] flags_val; wire[1:0] flags_out;
wire flags_lda; wire flags_lda;
wire flags_ldb; wire flags_ldb;
wire flags_ldc; wire flags_ldc;
flags flags( flags flags(
// In
.clk(clk), .clk(clk),
.a(a_val), .rst(rst),
.b(b_val), .a(a_out),
.c(c_val), .b(b_out),
.c(c_out),
.load_a(flags_lda), .load_a(flags_lda),
.load_b(flags_ldb), .load_b(flags_ldb),
.load_c(flags_ldc), .load_c(flags_ldc),
.out(flags_out)
// Out
.out(flags_val)
); );
controller controller( controller controller(
.clk(clk), .clk(clk),
.instr(ir_val), .rst(rst),
.flags(flags_val), .opcode(ir_out),
.ctrl_word({ .flags(flags_out),
.out({
hlt, hlt,
a_load, a_load, a_en, a_inc, a_dec,
a_en, b_load, b_en, b_inc, b_dec,
a_inc, c_load, c_en, c_inc, c_dec,
a_dec, flags_lda, flags_ldb, flags_ldc,
b_load, alu_op, alu_load, alu_en,
b_en,
b_inc,
b_dec,
c_load,
c_en,
c_inc,
c_dec,
flags_lda,
flags_ldb,
flags_ldc,
alu_op,
alu_load,
alu_en,
ir_load, ir_load,
pc_inc, pc_inc, pc_load, pc_en,
pc_load, mar_loadh, mar_loadl, mdr_load,
pc_en,
mar_loadh,
mar_loadl,
mdr_load,
mdr_en, mdr_en,
ram_load, ram_load, ram_enh, ram_enl,
ram_enh, call, ret})
ram_enl,
call,
ret})
); );
endmodule endmodule