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2023-fpga-computer/src/sap1/pc.v

22 lines
233 B
Verilog

module pc(
input clk,
input rst,
input inc,
output[7:0] out
);
reg[3:0] pc;
always @(posedge clk, posedge rst) begin
if (rst) begin
pc <= 4'b0;
end else if (inc) begin
pc <= pc + 1;
end
end
assign out = pc;
endmodule