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2023-fpga-computer/src/sap2/ir.v

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module ir(
input clk,
input rst,
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input load,
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input[15:0] bus,
output[7:0] out
);
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reg[7:0] ir;
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always @(posedge clk, posedge rst) begin
if (rst) begin
ir <= 8'b0;
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end else if (load) begin
ir <= bus[7:0];
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end
end
assign out = ir;
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endmodule