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2023-fpga-computer
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Update pin constraint file

This commit is contained in:
Austin Morlan 2023-03-04 17:57:05 -08:00
parent 3c0263fc05
commit c43955f8e8
Signed by: austin
GPG Key ID: FD6B27654AF5E348
3 changed files with 12 additions and 3 deletions
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2
build.sh
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@ -69,7 +69,7 @@ if [ -z "$COMMAND" ]; then
mkdir -p $BUILD_DIR/sap3
pushd $BUILD_DIR/sap3 > /dev/null
$BIN_DIR/yosys -p "synth_ice40 -json hardware.json" $SAP3_MODULES $SAP3_TOP
$BIN_DIR/yosys -q -p "synth_ice40 -json hardware.json" $SAP3_MODULES $SAP3_TOP
$BIN_DIR/nextpnr-ice40 --lp8k --package cm81 --json hardware.json --asc hardware.asc --pcf $SRC_DIR/pins.pcf -q
$BIN_DIR/icepack hardware.asc hardware.bin

11
src/pins.pcf
View File

@ -1,2 +1,11 @@
set_io --warn-no-port CLK B2 # input
set_io --warn-no-port CLK B2 # input
set_io --warn-no-port PIN_24 A6 # input
set_io --warn-no-port PIN_4 C2 # output
set_io --warn-no-port PIN_5 C1 # output
set_io --warn-no-port PIN_6 D2 # output
set_io --warn-no-port PIN_7 D1 # output
set_io --warn-no-port PIN_8 E2 # output
set_io --warn-no-port PIN_9 E1 # output
set_io --warn-no-port PIN_10 G2 # output
set_io --warn-no-port PIN_11 H1 # output

2
src/sap3/top.v
View File

@ -24,7 +24,7 @@ always @(posedge clk, posedge rst) begin
end
end
reg[18:0] bus;
reg[15:0] bus;
always @(*) begin
bus = 16'b0;